Other Parts Discussed in Thread: C2000WARE
Tool/software: Code Composer Studio
hello,
i want to configure trip zone for over current protection. below is my trip zone code for PWM1 but when i run this code there is no duty cycle i followed all right steps but i can not figure it out where is problem.
__interrupt void epwm1_tzint_isr(void);
void main(void)
{
InitSysCtrl();
InitFlash();
CpuSysRegs.PCLKCR2.bit.EPWM1=1;
InitEPwm1Gpio();
EALLOW;
GpioCtrlRegs.GPAPUD.bit.GPIO12 = 0; // Enable pullup on GPIO12
GpioCtrlRegs.GPAQSEL1.bit.GPIO12 = 3; // asynch input
GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 1; // GPIO12 = TZ1
EDIS;
InitPieCtrl();
IER = 0x0000;
IFR = 0x0000;
InitPieVectTable();
EALLOW;
PieVectTable.TIMER1_INT = &cpu_timer1_isr;
PieVectTable.ADCA1_INT = &adca1_isr;
PieVectTable.EPWM1_TZ_INT = &epwm1_tzint_isr;
EDIS;
EALLOW;
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC =0;
EDIS;
InitEPwm1Example();
ConfigureADC();
SetupADCEpwm();
EALLOW;
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC =1;
EDIS;
IER |= M_INT2;
IER |= M_INT3; // Enable CPU INT3 which is connected to EPWM1-3 INT EPWM4-6 INT:
PieCtrlRegs.PIEIER2.bit.INTx1 = 1;
InitCpuTimers();
ConfigCpuTimer(&CpuTimer1, 200, 20);//
CpuTimer1Regs.TCR.all = 0x4000;
PieCtrlRegs.PIEIER1.bit.INTx1 = 1;
PID_GRANDO_F_init(&V_Controller);
V_Controller.param.Kp = KP_V;
V_Controller.param.Ki = KI_V;
V_Controller.param.Kd = KD_V;
V_Controller.param.Umax = UMAX_V;
V_Controller.param.Umin = UMIN_V;
PID_GRANDO_F_init(&I_Controller);
I_Controller.param.Kp = KP_I;
I_Controller.param.Ki = KI_I;
I_Controller.param.Kd = KD_I;
I_Controller.param.Umax = UMAX_I;
I_Controller.param.Umin = UMIN_I;
AdcaRegs.ADCPPB1CONFIG.bit.CONFIG = 0; // Setup the post-processing` block to be associated with SOC0
IER |= M_INT1;
IER |= M_INT13;
for(;;)
{
asm(" NOP");
}
}
interrupt void adca1_isr(void)
{
if (k>=1000)
{
k=0;
}
else
k++;
//Samlped voltage and current
i1=((float)(AdcaResultRegs.ADCRESULT1)-2238)*0.012;
v1=((float)(AdcaResultRegs.ADCRESULT3)-2238)*0.035;
ia[0]=ia[1];
ia[1]=ia[2];
ia[2]=(ia[0]+ia[1]+i1)/3;
vo[0]=vo[1];
vo[1]=vo[2];
vo[2]=(vo[0]+vo[1]+v1)/3;
V_Controller.term.Ref = Vpeak_Ref*sintheta;
V_Controller.term.Fbk =vo[2];
V_Controller.term.c1 = 0;
V_Controller.term.c2 = 0;
PID_GRANDO_F_FUNC(&V_Controller);
I_Controller.term.Ref = V_Controller.term.Out;
I_Controller.term.Fbk = ia[2];
I_Controller.term.c1 = 0;
I_Controller.term.c2 = 0;
PID_GRANDO_F_FUNC(&I_Controller);
d= (V_Controller.term.Out)*0.6;
CMP = PERIOD*((1+d)/2);
EPwm1Regs.CMPA.bit.CMPA = CMP;
AdcaRegs.ADCINTFLGCLR.bit.ADCINT1 = 1;
PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
}
interrupt void epwm1_tzint_isr(void)
{
// Leave these flags set so we only take this
// interrupt once
//
EALLOW;
EPwm1Regs.TZCLR.bit.OST = 1;
EPwm1Regs.TZCLR.bit.INT = 1;
EDIS;
// Acknowledge this interrupt to receive more interrupts from group 2
PieCtrlRegs.PIEACK.all = PIEACK_GROUP2;
}
void InitEPwm1Example()
{
EALLOW;
EPwm1Regs.TZSEL.bit.OSHT1 = 1;
EPwm1Regs.TZSEL.bit.OSHT2 = 1;
// What do we want the TZ1 to do?
EPwm1Regs.TZCTL.bit.TZA = TZ_FORCE_LO;
EPwm1Regs.TZCTL.bit.TZB = TZ_FORCE_LO;
// Enable TZ interrupt
EPwm1Regs.TZEINT.bit.OST = 0;
EDIS;
//
// Setup TBCLK
//
EPwm1Regs.TBPRD = PERIOD ; // Set timer period
EPwm1Regs.TBPHS.bit.TBPHS = 0x0000; // Phase is 0
EPwm1Regs.TBCTR = 0x0000; // Clear counter
//
// Setup counter mode
//
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; // Sync output is equal to zero
//
// Setup shadowing
//
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // Load on Zero
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
//
// Setup compare
//
EPwm1Regs.CMPA.bit.CMPA = 0; //
// EPwm1Regs.CMPB.bit.CMPB = 0;
//
// Set actions
EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR; // EPW1A
EPwm1Regs.AQCTLA.bit.CAD = AQ_SET; // EPW1A
EPwm1Regs.AQCTLB.bit.CAU = AQ_SET;
EPwm1Regs.AQCTLB.bit.CAD = AQ_CLEAR; // EPW1B
// EPW1B
//
// Interrupt where we will change the Compare Values
//
EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event INTSEL= interrupt selection
EPwm1Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm1Regs.ETPS.bit.INTPRD = ET_1ST; // Generate INT on 1st event
//Start Conversion of ADC
EPwm1Regs.ETSEL.bit.SOCAEN = 1; // Enable SOC on A group
EPwm1Regs.ETSEL.bit.SOCASEL = 2;
EPwm1Regs.ETPS.bit.SOCAPRD = 1; // Generate pulse on 1st event
}