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CCS/TMS320F28375D: 2 CPU environment EMIF setting

Part Number: TMS320F28375D


Tool/software: Code Composer Studio

Can you tell me how EMIF works in a dual cpu environment using C28?

The environment is as follows.
- TMS320F28375D
- CCS 8.1.0.00011

The pins of GPIO connected by EMIF are as follows.
- EM1 WE
- EM1 RNW
- EM1 CS2
- EM1 CS3
- EM1 WAIT
- EM1 OE
- EM1 A0-A15
- EM1 D0-D15
- EM1 BA0


[Question1]
-Both CPU1 and 2 are trying to write data to the external memory of CS2 through EMIF1 using GPIO.
-GPIO used for EMIF is set to "CPU1" with the "GPIO_SetupPinMux ()" function.
-CPU1 can access the external memory and is ready to read and write.

Under the above conditions,
Is it necessary to change GPIO_SetupPinMux () every time CPU2 side accesses external memory?
need another line and GPIO?


[Question2]
-Both CPU1 and 2 are trying to write data to the external memory of CS2 through EMIF1 using GPIO.
-GPIO used for EMIF is set to "CPU2" with the "GPIO_SetupPinMux ()" function.
-CPU2 side is in the same EMIF setting as CPU1. (Probably)

In the above case,
The external memory can be accessed from CPU1 for some reason and it is in a rewritable state.
When the external memory is accessed in the main function on the CPU2 side, it is in the ReadOnly state.
How can I make the CPU2 side writable?

Sorry for the poor English.
Thanks and regards.

  • Hi,

    Thanks for detailed explanation about your queries.

    Is it necessary to change GPIO_SetupPinMux () every time CPU2 side accesses external memory?

    GPIO pinmux is independent of which CPU accessing the EMIF. READs are always allowed from both CPU but WRITEs are allowed from one CPU only based on master select configuration in EMIF1MSEL register. You need to change this to allow other CPU to have write access.

    I think this answers all your queries.

    On the EMIF pin connection, since you are connecting WE and OE, I am wondering what RNW is used for in this case?

    Regards,

    Vivek Singh

  • Thank you for your answer.
    If it was corrected based on the answer, it worked normally.

    EMIF1MSEL.all is misused and
    Instead of calling once when the CPU starts up, it was necessary to reset each EMIF processing of each CPU.

    Thank you very much.