• State Resolved
  • Locked Locked
  • Replies 2 replies
  • Subscribers 81 subscribers
  • Views 400 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

Concerto M3 can use adc ?

F28M35H52C: ADC Interrupt on M3 side

Erik Iverson
Prodigy 180 points

Part Number: F28M35H52C

The documentation says the M3 NVIC can handle interrupts from the Analog subsystem. 

SPRUH22F section 11.3.7 : The ADC contains eight interrupts that can be flagged and/or passed on to the PIE and NVIC.

The ADC interrupts are indeed defined in MWare\inc\hw_ints.h. 

On the C28, I configure ADCINT2 as I want it:

Adc2Regs.INTSEL1N2.bit.INT2E = 1; // Enabled ADCINT2
Adc2Regs.INTSEL1N2.bit.INT2CONT=1; //Enable ADCINT2 Continuous mode, also tried non-continuous mode
Adc2Regs.INTSEL1N2.bit.INT2SEL = 0xE; // setup EOC14 to trigger ADCINT2 for M3

On the M3, I use the driverlib for NVIC:

    //Setup the interrupts for the ADC EOC14 interrupt:
    IntEnable(INT_ADC2);
    IntRegister(INT_ADC2, ADCHandler);
    // Enable processor interrupts.
    IntMasterEnable();

Where ADCHandler is the callback I've defined. 

It is unclear to me how to acknowledge the interrupt from the M3 side. Should I use IntPendClear(INT_ADC2)? 

Since the C28 PIE doesn't handle the interrupt, it doesn't seem like I should have to acknowledge the interrupt on the C28. But do I? Do I need to do anything else with the PIE?

When I do use the above code with IntPendClear(INT_ADC2) called in ADCHandler, the cores don't really run in the debugger and something keeps resetting them. 

Previously I had a working example with the ADC Interrupt 1 executing on the C28 side. But I've been unsucessful getting an ADC interrupt to execute on the M3 side. 

Ricky's last post on this thread: https://e2e.ti.com/support/microcontrollers/c2000/f/171/t/138792?Concerto-M3-can-use-adc- says what I'm trying should be possible. 

Thanks. -Erik

  • 0
    Prodigy 180 points

    Actually, I got my example working. The cores were resetting because I forgot to SysCtlPeripheralEnable() before I GPIOPinConfigureCoreSelect(). On the C28, I found that Adc2Regs.INTSEL1N2.bit.INT2CONT=1; was necessary, and with continuous mode disabled, the M3 ISR was only called once. So I'm not sure I am clearing/acknowledging the interrupt. But nonetheless it seems to be working, so maybe the clearing/acknowledging doesn't matter?

  • 0 in reply to Erik Iverson
    TI__Guru 62975 points

    Erik,

    I'm glad that you were able to get the interrupts working.

    There are two levels of interrupt servicing when using the ADC interrupts. The first level is within the ADC and the second level is at the SoC interrupt handling.

    ADC Level

    The ADC itself relies on interrupt servicing (through ADCINTFLGCLR) to detect interrupt overflows. Once an overflow state is encountered the ADC will not generate further interrupts until the overflow and interrupt flags have been cleared.

    In the case of C28x servicing of ADC interrupts, it is easy to clear the interrupt flag from the C28x ISR. This is more difficult in the case of M3 servicing ADC interrupts because the M3 does not have access to the ADC configuration registers so it is not possible to directly clear the interrupt flag from the M3 ISR. The ADC would need to be serviced by the C28x through a multi-core scheme, or the ADC can be placed into continuous mode so that the servicing requirement (and overflow detection) is removed.

    SoC Level

    All interrupts at the SoC level need to be serviced in the ISR according to the requirements of the enabled interrupt path (C28x PIE and/or M3 NVIC) for proper operation.

    -Tommy