Part Number: TMS320F28377S
Other Parts Discussed in Thread: C2000WARE
Hello,
I'm using SPI in master mode.
I need for write access to an external chip to send the address (16bits) and then the data to write (16bits)
To do this, the simplified code written is like following:
Toggle GPIO
SPI_TXBUB = Addr /* Start the sending of address word */
while (SPI_RXFFST == 0){} /* Wait the end of transmission */
dummy = SPI_RXBUF /* dummy read to empty fifo */
Toggle GPIO
SPI_TXBUB = Data /* Start the sending of address word */
while (SPI_RXFFST == 0){} /* Wait the end of transmission */
dummy = SPI_RXBUF /* dummy read to empty fifo */
Toggle GPIO
The scope screenshot of Clock signal and GPIO toggled is like following:
The SPI CLK is set to 20MHz, the 16 bits take about 800ns. But between the two data, there are about 380ns, this is about the half time to transmit a 16 bits word!...
The instruction time between the wait of the last transmission and the tri of the new not explain this time.
The time between the instruction which set the TXBUF register and the real start of the transmission is about 200ns!..
The time between the end of transmission ans the flag bit RXFifo is also about 200ns..
Is these time are ok or something in my case is bad?
Bellow is my init code:
/* Hold Reset bit during initialization */
SpiRegs[Channel]->SPICCR.bit.SPISWRESET = 0;
/* Set clock polarity and 16 bit character */
SpiRegs[Channel]->SPICCR.all = SPI_CCR_CLK_POL_PHA_MODE3 | SPI_CCR_NB_CHAR(16);
SpiRegs[Channel]->SPICCR.bit.HS_MODE = ActivateHighSpeed;
/* Set Clock Phase, Master mode, Enable transmitter */
SpiRegs[Channel]->SPICTL.all = SPI_CTL_CLK_POL_PHA_MODE3 | SPI_CTL_MODE_MASTER | SPI_CTL_TRANSMIT_ENABLE;
SpiRegs[Channel]->SPISTS.all = 0x0000;
/* Set baud rate: Spi Baud Rate = LSPCLK / (SPIBRR+1) */
DV_Spi_SetBaudRate(BasePtr, (MAIN_LOW_SPEED_PERIPHERAL_FREQUENCY_MHZ / DV_SPI_BAUD_RATE_MHZ) - 1);
/* No FIFO used */
SpiRegs[Channel]->SPIFFTX.all = 0xE040;
SpiRegs[Channel]->SPIFFRX.all = 0x2044;
SpiRegs[Channel]->SPIFFCT.all = 0x00;
/* Free Run mode */
SpiRegs[Channel]->SPIPRI.bit.FREE = 1;
/* Enable SPI */
SpiRegs[Channel]->SPICCR.bit.SPISWRESET = 1;
/* Empty the Fifo */
DV_Spi_EmptyFifo(BasePtr);
-------
#define DV_Spi_EmptyFifo(Base) \
{ \
volatile uint16_t Dummy; \
\
while((HWREGH(Base + SPI_O_FFRX) & SPI_FFRX_RXFFST_M) != 0) \
{ \
Dummy = DV_Spi_iGetRxBuffer((Base)); \
} \
}
Thank
