Other Parts Discussed in Thread: CONTROLSUITE, TIDA-01606
Tool/software: Code Composer Studio
Hi, I am trying to incorporate PLL in SVPWM code. I am following the incremental build level 3 of this example
C:\ti\controlSUITE\development_kits\HVMotorCtrl+PfcKit_v2.0\HVACI_Sensored for SVPWM generation. I am able to generate all the required PWM signals using this example in open loop without PLL.
Now I am trying to incorporate 3-phase PLL into this code. I am using SPLL_3ph_SRF for PLL. Now when I use angle from PLL i.e. spll1.theta instead of ramp generator's output i.e. rg1.out in inverse Park Transformation, then SVPWM does not work anymore. Please see the image attached for clarification on what I am trying to do exactly.
Please find attached c-file of my code. I am sensing three phase input from AC source, performing Clarke and Park Transformations on it to achieve Vq. Then I use this Vq in SPLL to generate theta. When I am using this theta instead of rg1.out, my SVPWM does not work anymore.
Please let me know what how can I achieve PLL correctly along with SVPWM.
//###########################################################################
//
// FILE: control_cpu01.c
//
// TITLE: Inverter Control (SVPWM)
//
//!
//!
//!
//###########################################################################
//
// Included Files
#define MATH_TYPE FLOAT_MATH //IQ_MATH
#include "IQmathLib.h"
#include <math.h>
#include "F28x_Project.h"
#include "settings.h"
#include "Solar_F.h"
//#include "Solar_IQ.h"
// Create an instance of DATALOG Module
DLOG_4CH_F dlog_4ch1;
// Create an instance of PLL Module
SPLL_3ph_SRF_F spll1;
//SPLL_3ph_SRF_IQ spll1;
// Create an instance of ABCtoDQ module
ABC_DQ0_POS_F abc_dq0_pos1;
// Function Prototypes
void InitEPwm(void);
void ConfigureADC(void);
__interrupt void epwm1_isr(void);
__interrupt void adca1_isr(void);
Uint16 usPwmPeriod;
Uint16 EPwm1_DB;
Uint16 EPwm2_DB;
Uint16 EPwm3_DB;
Uint16 usPwm2Phase;
Uint16 usPwm3Phase;
Uint16 EPwm1_CMP;
Uint16 EPwm2_CMP;
Uint16 EPwm3_CMP;
float32 fDutyCycle;
float32 fTdb;
float32 fTdb2;
float32 fTdb3;
// ADC values
float32 fVa;
float32 fVb;
float32 fVc;
float32 fVd;
float32 fScale1;
float32 fScale2;
float32 fScale3;
float32 fScale4;
float32 fOffset1;
float32 fOffset2;
float32 fOffset3;
float32 fOffset4;
// Variables for viewing signals in CCS graph
#define RESULTS_BUFFER_SIZE 128
int16 Adc1[RESULTS_BUFFER_SIZE];
int16 Adc2[RESULTS_BUFFER_SIZE];
int16 Adc3[RESULTS_BUFFER_SIZE];
int16 Adc4[RESULTS_BUFFER_SIZE];
//int16 Adc5[RESULTS_BUFFER_SIZE];
//int16 Adc6[RESULTS_BUFFER_SIZE];
//int16 Adc7[RESULTS_BUFFER_SIZE];
//int16 Adc8[RESULTS_BUFFER_SIZE];
Uint16 resultsIndex;
Uint16 saveIndex;
volatile Uint16 bufferFull;
Uint16 usStartSaveData;
Uint16 samplePace;
// ****************************************************************************
// Variables for MACROS
// ****************************************************************************
float32 T = 0.001/ISR_FREQUENCY; // Samping period (sec), see parameter.h
_iq VdTesting = _IQ(1.0), // Vd reference (pu)
VqTesting = _IQ(0.0), // Vq reference (pu)
IdRef = _IQ(0.0), // Id reference (pu)
IqRef = _IQ(0.0), // Iq reference (pu)
SpeedRef = _IQ(1.0), // For Closed Loop tests
lsw1Speed = _IQ(0.02); // initial force rotation speed in search of QEP index pulse
// Instance a few transform objects (ICLARKE is added into SVGEN module)
//CLARKE clarke1 = CLARKE_DEFAULTS;
//PARK park1 = PARK_DEFAULTS;
IPARK ipark1 = IPARK_DEFAULTS;
//PHASEVOLTAGE volt1 = PHASEVOLTAGE_DEFAULTS;
// Instance a Space Vector PWM modulator. This modulator generates a, b and c
// phases based on the d and q stationery reference frame inputs
SVGENDPWM_240 svgen1 = SVGENDPWM_240_DEFAULTS;
//SVGEN svgen1 = SVGEN_DEFAULTS;
// Instance a ramp controller to smoothly ramp the frequency
RMPCNTL rc1 = RMPCNTL_DEFAULTS;
// Instance a ramp(sawtooth) generator to simulate an Anglele
RAMPGEN rg1 = RAMPGEN_DEFAULTS;
CLARKE clarke1 = CLARKE_DEFAULTS;
PARK park1 = PARK_DEFAULTS;
// ****************************************************************************
// Variables for Datalog module
// ****************************************************************************
float DBUFF_4CH1[200],
DBUFF_4CH2[50],
DBUFF_4CH3[50],
DBUFF_4CH4[50],
DlogCh1,
DlogCh2,
DlogCh3,
DlogCh4;
void Shutdown(void);
//
// Main
//
void main(void)
{
InitSysCtrl();
rg1.StepAngleMax = _IQ(GRID_FREQ*T);
//
// enable PWM1,2 and PWM3
//
CpuSysRegs.PCLKCR2.bit.EPWM1 = 1;
CpuSysRegs.PCLKCR2.bit.EPWM2 = 1;
CpuSysRegs.PCLKCR2.bit.EPWM3 = 1;
//
// For this case just init GPIO pins for ePWM1
// These functions are in the F2837xD_EPwm.c file
//
InitEPwm1Gpio();
InitEPwm2Gpio();
InitEPwm3Gpio();
EALLOW;
GpioCtrlRegs.GPAMUX1.bit.GPIO8 = 0; // GPIO
GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 0; // GPIO
GpioCtrlRegs.GPADIR.bit.GPIO8 = 1; // output
GpioCtrlRegs.GPADIR.bit.GPIO10 = 1; // output
EDIS;
DINT;
InitPieCtrl();
IER = 0x0000;
IFR = 0x0000;
InitPieVectTable();
//
// Interrupts that are used in this example are re-mapped to
// ISR functions found within this file.
//
EALLOW; // This is needed to write to EALLOW protected registers
PieVectTable.EPWM1_INT = &epwm1_isr;
PieVectTable.ADCA1_INT = &adca1_isr; //function for ADCA interrupt 1
EDIS; // This is needed to disable write to EALLOW protected registers
// Configure the ADC and power it up
// Setup the ADC for ePWM triggered conversions
// ************ SHOULD BE DONE BEFORE PWM CONFIG **************
ConfigureADC();
//
// Step 4. Initialize the Device Peripherals:
//
EALLOW;
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC =0;
EDIS;
InitEPwm();
EALLOW;
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC =1;
EDIS;
SPLL_3ph_SRF_F_init(GRID_FREQ,((float)(1.0/ISR_FREQUENCY)),&spll1);
//SPLL_3ph_SRF_IQ_init(GRID_FREQ,_IQ21((float)(1.0/ISR_FREQUENCY)),&spll1);
//
// Step 5. User specific code
// Initialize variables
// ****************************************************
// Initialize DATALOG module
// ****************************************************
DLOG_4CH_F_init(&dlog_4ch1);
dlog_4ch1.input_ptr1 = &DlogCh1; //data value
dlog_4ch1.input_ptr2 = &DlogCh2;
dlog_4ch1.input_ptr3 = &DlogCh3;
dlog_4ch1.input_ptr4 = &DlogCh4;
dlog_4ch1.output_ptr1 = &DBUFF_4CH1[0];
dlog_4ch1.output_ptr2 = &DBUFF_4CH2[0];
dlog_4ch1.output_ptr3 = &DBUFF_4CH3[0];
dlog_4ch1.output_ptr4 = &DBUFF_4CH4[0];
dlog_4ch1.size = 200;
dlog_4ch1.pre_scalar = 5;
dlog_4ch1.trig_value = 0.01;
dlog_4ch1.status = 2;
for(resultsIndex = 0; resultsIndex < RESULTS_BUFFER_SIZE; resultsIndex++)
{
Adc1[resultsIndex] = 0;
Adc2[resultsIndex] = 0;
Adc3[resultsIndex] = 0;
Adc4[resultsIndex] = 0;
}
resultsIndex = 0;
saveIndex = 0;
bufferFull = 0;
samplePace = 2;
usStartSaveData = 0;
fScale1 = 800;
fScale2 = 800;
fScale3 = 800;
fScale4 = 800;
fOffset1 = 0;
fOffset2 = -1;
fOffset3 = -1;
fOffset4 = -1;
//
// Enable CPU INT3 which is connected to EPWM1-3 INT:
//
IER |= M_INT3;
IER |= M_INT1; // for ADC isr
EINT; // Enable Global interrupt INTM
ERTM; // Enable Global realtime interrupt DBGM
//
// Enable PIE interrupt
//
PieCtrlRegs.PIEIER3.bit.INTx1 = 1; // PWM
PieCtrlRegs.PIEIER1.bit.INTx1 = 1; // ADC isr
// conv_duty();
for(;;)
{
asm (" NOP");
}
}
//
// epwm1_isr - EPWM1 ISR
//
__interrupt void epwm1_isr(void)
{
GpioDataRegs.GPASET.bit.GPIO8 = 1; // Pin 57
asm (" NOP"); asm (" NOP");
asm (" NOP"); asm (" NOP");
asm (" NOP"); asm (" NOP");
asm (" NOP"); asm (" NOP");
asm (" NOP"); asm (" NOP");
EPwm2Regs.TBPHS.bit.TBPHS = usPwm2Phase;
EPwm3Regs.TBPHS.bit.TBPHS = usPwm3Phase;
// EPwm1Regs.TBPRD = usPwmPeriod;
// EPwm2Regs.TBPRD = usPwmPeriod;
// EPwm3Regs.TBPRD = usPwmPeriod;
GpioDataRegs.GPACLEAR.bit.GPIO8 = 1;
// Clear INT flag for this timer
EPwm1Regs.ETCLR.bit.INT = 1;
// Acknowledge this interrupt to receive more interrupts from group 3
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
}
//
// adca1_isr - Read ADC Buffer in ISR
//
__interrupt void adca1_isr(void)
{
//**********************************************
// Get ADC Results
//**********************************************
fVd = fScale1 * (((float32)AdcaResultRegs.ADCRESULT0) * 0.0007326007326 + fOffset1);
fVa = fScale2 * (((float32)AdcaResultRegs.ADCRESULT1) * 0.0007326007326 + fOffset2);
fVb = fScale3 * (((float32)AdcaResultRegs.ADCRESULT2) * 0.0007326007326 + fOffset3);
fVc = fScale4 * (((float32)AdcaResultRegs.ADCRESULT3) * 0.0007326007326 + fOffset4);
/* abc_dq0_pos1.a = fVa;
abc_dq0_pos1.b = fVb;
abc_dq0_pos1.c = fVc;
abc_dq0_pos1.sin = __sinpuf32((spll1.theta[1]));
abc_dq0_pos1.cos = __cospuf32((spll1.theta[1]));
ABC_DQ0_POS_F_MACRO(abc_dq0_pos1);
spll1.v_q[0] = (abc_dq0_pos1.q);
*/
// SPLL_3ph_SRF_F_FUNC(&spll1);
// SPLL_3ph_SRF_F_MACRO(spll1); // takes less time
GpioDataRegs.GPASET.bit.GPIO10 = 1; // Pin 61
// ------------------------------------------------------------------------------
// Connect inputs of the RMP module and call the ramp control macro
// ------------------------------------------------------------------------------
rc1.TargetValue = SpeedRef;
RC_MACRO(rc1)
// ------------------------------------------------------------------------------
// Connect inputs of the RAMP GEN module and call the ramp generator macro
// ------------------------------------------------------------------------------
rg1.Freq = rc1.SetpointValue;
RG_MACRO(rg1)
/*
// ------------------------------------------------------------------------------
// Measure phase currents, subtract the offset and normalize from (-0.5,+0.5) to (-1,+1).
// Connect inputs of the CLARKE module and call the clarke transformation macro
// ------------------------------------------------------------------------------
clarke1.As = fVa; // Phase A Voltage
clarke1.Bs = fVb;// Phase B Voltage
CLARKE_MACRO(clarke1)
// ------------------------------------------------------------------------------
// Connect inputs of the PARK module and call the park trans. macro
// ------------------------------------------------------------------------------
park1.Alpha = clarke1.Alpha;
park1.Beta = clarke1.Beta;
park1.Angle = rg1.Out;
park1.Sine = __sinpuf32(park1.Angle);
park1.Cosine = __cospuf32(park1.Angle);
PARK_MACRO(park1)
spll1.v_q[0] = park1.Qs;
SPLL_3ph_SRF_F_MACRO(spll1); // takes less time
// ------------------------------------------------------------------------------
// Connect inputs of the INV_PARK module and call the inverse park trans. macro
// There are two option for trigonometric functions:
// IQ sin/cos look-up table provides 512 discrete sin and cos points in Q30 format
// IQsin/cos PU functions interpolate the data in the lookup table yielding higher resolution.
// ------------------------------------------------------------------------------
*/
ipark1.Ds = VdTesting;
ipark1.Qs = VqTesting;
// ipark1.Sine = __sinpuf32(spll1.theta[1]);
// ipark1.Cosine = __cospuf32(spll1.theta[1]);
ipark1.Sine=__sinpuf32(rg1.Out);
ipark1.Cosine=__cospuf32(rg1.Out);
IPARK_MACRO(ipark1)
// ------------------------------------------------------------------------------
// Connect inputs of the SVGEN module and call the space-vector gen. macro
// ------------------------------------------------------------------------------
svgen1.Ualpha = ipark1.Alpha;
svgen1.Ubeta = ipark1.Beta;
SVGENDPWM_240_MACRO(svgen1)
//SVGENDQ_MACRO(svgen1)
// ------------------------------------------------------------------------------
// Computed Duty and Write to CMPA register
// ------------------------------------------------------------------------------
EPwm1Regs.CMPA.bit.CMPA = (INV_PWM_HALF_TBPRD*svgen1.Tc)+INV_PWM_HALF_TBPRD;
EPwm2Regs.CMPA.bit.CMPA = (INV_PWM_HALF_TBPRD*svgen1.Ta)+INV_PWM_HALF_TBPRD;
EPwm3Regs.CMPA.bit.CMPA = (INV_PWM_HALF_TBPRD*svgen1.Tb)+INV_PWM_HALF_TBPRD;
// Connect inputs of the DATALOG module
/* DlogCh1 = rg1.Out;
DlogCh2 = svgen1.Ta;
DlogCh3 = svgen1.Tb;
DlogCh4 = DlogCh2 - DlogCh3;
*/
DlogCh1 = fVa;
DlogCh2 = fVb;
DlogCh3 = fVc;
DlogCh4 = fVd;
// ------------------------------------------------------------------------------
// Call the DATALOG update function.
// ------------------------------------------------------------------------------
DLOG_4CH_F_FUNC(&dlog_4ch1);
//**********************************************
// View data in CCS graph
//**********************************************
if( usStartSaveData == 1 )
{
saveIndex++;
if( (bufferFull == 0) && (samplePace <= saveIndex) )
{
Adc1[resultsIndex] = fVb;
Adc2[resultsIndex] = fVa;
Adc3[resultsIndex] = fVc;
Adc4[resultsIndex] = fVd;
resultsIndex++;
saveIndex = 0;
}
if(RESULTS_BUFFER_SIZE <= resultsIndex)
{
resultsIndex = 0;
bufferFull = 1;
saveIndex = 0;
usStartSaveData = 0;
}
}
GpioDataRegs.GPACLEAR.bit.GPIO10 = 1; // Pin 61
AdcaRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; //clear INT1 flag
PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
}
//
// InitEPwm - Initialize EPWMx configuration
//
void InitEPwm()
{
// fDuty = 0.5;
fTdb = 100; // ns
fTdb2 = 100;//100.0; // ns
fTdb3 = 100.0; // ns
EPwm1_DB = (Uint16)(fTdb * 0.1);
EPwm2_DB = (Uint16)(fTdb2 * 0.1);
EPwm3_DB = (Uint16)(fTdb3 * 0.1);
usPwm2Phase = 0;
usPwm3Phase = 0;
EPwm1Regs.TBPRD = PWM_PRD_UD; // Set timer period
EPwm1Regs.TBPHS.bit.TBPHS = 0x0000; // Phase is 0
EPwm1Regs.TBCTR = 0x0000; // Clear counter
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up-down
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm1Regs.TBCTL.bit.SYNCOSEL = 1; // Sync Output Select: CTR = zero
EPwm1Regs.rsvd2[0] = 0x0002; // EPWMxSYNCOUT Source Enable Register
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load registers every ZERO
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
// EPwm1Regs.CMPA.bit.CMPA = (Uint16)(fDutyCycle * (float32)PWM_PRD_UD);
EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Set PWM1A on Zero
EPwm1Regs.AQCTLA.bit.CAD = AQ_SET;
EPwm1Regs.AQCTLB.bit.CAU = AQ_SET; // Set PWM1A on Zero
EPwm1Regs.AQCTLB.bit.CAD = AQ_CLEAR;
EPwm1Regs.AQSFRC.bit.RLDCSF = 3; // Load immediately
EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
EPwm1Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm1Regs.DBRED.bit.DBRED = EPwm1_DB;
EPwm1Regs.DBFED.bit.DBFED = EPwm1_DB;
EPwm2Regs.TBPRD = PWM_PRD_UD; // Set timer period
EPwm2Regs.TBPHS.bit.TBPHS = usPwm2Phase; // Phase is 0
EPwm2Regs.TBCTR = 0x0000; // Clear counter
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up-down
EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Disable phase loading
EPwm2Regs.TBCTL.bit.PHSDIR = TB_UP;
EPwm2Regs.TBCTL.bit.SYNCOSEL = 0;
EPwm2Regs.rsvd2[0] = 0x0002; // EPWMxSYNCOUT Source Enable Register
EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load registers every ZERO
EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
//EPwm2Regs.CMPA.bit.CMPA = (Uint16)(fDutyCycle * (float32)PWM_PRD_UD);
EPwm2Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Set PWM1A on Zero
EPwm2Regs.AQCTLA.bit.CAD = AQ_SET;
EPwm2Regs.AQCTLB.bit.CAU = AQ_CLEAR; // Set PWM1A on Zero
EPwm2Regs.AQCTLB.bit.CAD = AQ_SET;
EPwm2Regs.AQSFRC.bit.RLDCSF = 3; // Load immediately
EPwm2Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
EPwm2Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm2Regs.DBRED.bit.DBRED = EPwm2_DB;
EPwm2Regs.DBFED.bit.DBFED = EPwm2_DB;
EPwm3Regs.TBPRD = PWM_PRD_UD; // Set timer period
EPwm3Regs.TBPHS.bit.TBPHS = usPwm3Phase; // Phase is 0
EPwm3Regs.TBCTR = 0x0000; // Clear counter
EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up-down
EPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Disable phase loading
EPwm3Regs.TBCTL.bit.PHSDIR = 1; // Count down/up (0/1) after the synchronization event
//EPwm3Regs.TBCTL.bit.PHSDIR = 0; // down for sampling instant in one phase test
EPwm3Regs.TBCTL.bit.SYNCOSEL = 0;
EPwm3Regs.rsvd2[0] = 0x0002; // EPWMxSYNCOUT Source Enable Register
EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load registers every ZERO
EPwm3Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm3Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
//EPwm3Regs.CMPA.bit.CMPA = (Uint16)(fDutyCycle * (float32)PWM_PRD_UD);
EPwm3Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Set PWM1A on Zero
EPwm3Regs.AQCTLA.bit.CAD = AQ_SET;
EPwm3Regs.AQCTLB.bit.CAU = AQ_SET; // Set PWM1A on Zero
EPwm3Regs.AQCTLB.bit.CAD = AQ_CLEAR;
EPwm3Regs.AQSFRC.bit.RLDCSF = 3; // Load immediately
EPwm3Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm3Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
EPwm3Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm3Regs.DBRED.bit.DBRED = EPwm3_DB;
EPwm3Regs.DBFED.bit.DBFED = EPwm3_DB;
// Interrupt setting
EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm1Regs.ETPS.bit.INTPRD = ET_1ST; // Generate INT on 1st event
EPwm1Regs.ETSEL.bit.INTEN = 1; // Enable INT
// ADC SOC
EALLOW;
EPwm1Regs.ETSEL.bit.SOCASEL = 1; // Select SOC on Zero
EPwm1Regs.ETSEL.bit.SOCAEN = 1; //enable SOCA
EPwm1Regs.ETPS.bit.SOCAPRD = ET_1ST; // Generate pulse on ___ event
EDIS;
}
//
// ConfigureADC - Write ADC configurations and power up the ADC for both
// ADC A and ADC B
//
void ConfigureADC(void)
{
Uint16 acqps;
EALLOW;
//write configurations
AdcaRegs.ADCCTL2.bit.PRESCALE = 2; //set ADCCLK divider to /2.0
AdcSetMode(ADC_ADCA, ADC_RESOLUTION_12BIT, ADC_SIGNALMODE_SINGLE);
//Set pulse positions to late
AdcaRegs.ADCCTL1.bit.INTPULSEPOS = 1;
//power up the ADC
AdcaRegs.ADCCTL1.bit.ADCPWDNZ = 1;
//delay for 1ms to allow ADC time to power up
DELAY_US(1000);
EDIS;
// Determine minimum acquisition window (in SYSCLKS) based on resolution
if(ADC_RESOLUTION_12BIT == AdcaRegs.ADCCTL2.bit.RESOLUTION)
{
acqps = 14; //75ns
}
else //resolution is 16-bit
{
acqps = 63; //320ns
}
//Select the channels to convert and end of conversion flag
EALLOW;
AdcaRegs.ADCSOC0CTL.bit.CHSEL = 0; //SOC0 will convert pin A0
AdcaRegs.ADCSOC0CTL.bit.ACQPS = acqps; //sample window is 100 SYSCLK cycles
AdcaRegs.ADCSOC0CTL.bit.TRIGSEL = ADCTRIG; //ADCTRIG9 - ePWM3, ADCSOCA, ADCTRIG5 - ePWM1, ADCSOCA
AdcaRegs.ADCSOC1CTL.bit.CHSEL = 1;
AdcaRegs.ADCSOC1CTL.bit.ACQPS = acqps;
AdcaRegs.ADCSOC1CTL.bit.TRIGSEL = ADCTRIG;
AdcaRegs.ADCSOC2CTL.bit.CHSEL = 2;
AdcaRegs.ADCSOC2CTL.bit.ACQPS = acqps;
AdcaRegs.ADCSOC2CTL.bit.TRIGSEL = ADCTRIG;
AdcaRegs.ADCSOC3CTL.bit.CHSEL = 3;
AdcaRegs.ADCSOC3CTL.bit.ACQPS = acqps;
AdcaRegs.ADCSOC3CTL.bit.TRIGSEL = ADCTRIG;
AdcaRegs.ADCSOC4CTL.bit.CHSEL = 4;
AdcaRegs.ADCSOC4CTL.bit.ACQPS = acqps;
AdcaRegs.ADCSOC4CTL.bit.TRIGSEL = ADCTRIG;
AdcaRegs.ADCSOC5CTL.bit.CHSEL = 5;
AdcaRegs.ADCSOC5CTL.bit.ACQPS = acqps;
AdcaRegs.ADCSOC5CTL.bit.TRIGSEL = ADCTRIG;
AdcaRegs.ADCINTSEL1N2.bit.INT1SEL = 5; //end of SOCx will set INT1 flag
AdcaRegs.ADCINTSEL1N2.bit.INT1E = 1; //enable INT1 flag
AdcaRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; //make sure INT1 flag is cleared
EDIS;
}
//
// End of file
//
