Tool/software: WEBENCH® Design Tools
Hello,
There seems to be a contradiction in the description of the RMII interface signals (F2838x TRM, section 42.2.1.2). Indeed, it says "The clock [RMII_REFCLK] is generated by the PHY (...). If External clocking option is selected this signal is input and if internal clock is selected, this signal is output." I believe that it should rather say that RMII_REFCLK is generated by the PHY in external clocking mode. Please confirm.
Also, it would be good that the names be consistent across the TRM and the datasheet as the latter refers to ENET_RMII_CLK.
Best regards,
François.
