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TMS320F280049: Dual Axis Drive System with 2 absolut encoder + Communication with SPI possible

Part Number: TMS320F280049
Other Parts Discussed in Thread: SN65HVD73, SN65HVD76, SN65HVD70, , C2000WARE

Hi

I'm thinking about using the TMS320F28004x Family for the development of a dual axis drive system with 2 absolut encoders. As far as i understood the SPI peripheral is needed (together with the CLB) to use the absolut encoder feature. Is it still posible to use 2 absolut encoders simultaniously with one SPI for normal communication?

Thanks for your help

  • The common encoders do not have any CS signal. Assuming RS422 interface, using RS422/485 full duplex transceivers with enable signals (such as SN65HVD70, SN65HVD73 or SN65HVD76) should be doable.

  • Sorry, I don't see the link between your answer and my question. I would use a RS422 transceiver to convert the differential signal to a "normal" signal. Something like you can see in the schematic of the BiSS-C Absolute Encoder Master Interface Reference Design is my plan ---> http://www.ti.com/lit/df/tidrst7/tidrst7.pdf

    Because there are only 2 SPI's available on the TMS320F280049 uC, and they seem to be used for the absolute encoder feature, my question is if you still can use one SPI for nomal communicatin. I assume it's not possible but maybe I have overseen something.

  • Sorry I was too terse.

    I'd connect two encoders to one SPI , where MCU would drive Enable signals for two transceivers via GPIO. This will leave you one SPI for normal communication.

  • Ah, now I see in which direction you're thinking. But I'm still a bit confused how you like to connect two encoders to one SPI. 

    If you have a look at the EnDat Implementation diagram I don't see a way to use two encoders with one SPI (MISO ond MOSI are both used for one Encoder). The enable signals for the two transceivers are already done with GPIO's.

    Could you explain further how you would connect them to one SPI?

    Thanks a lot for your effort!

  • Hi,

    Our current library supports only one absolute encoder like BiSS-C or ENDat22.
    There is no plan to support multiple encoders as of now. Our absolute encoder implementation is based on CLB (Configurable Logic Block).
    We'll be releasing a tool to configure CLB at the end of this month in the upcoming C2000Ware release.
    CLB resources will also be a limiting factor, besides SPI.
    If you are using other encoders like QEP or Sincos, you can create your own implementation.

  • Thanks for your answer. Why does the library only support one encoder? Does the hardware limit it or is it to much work to implement a library with multiple encoders. In the following document is written, that CLB should support two encoders:

    http://www.ti.com/lit/wp/sway022/sway022.pdf

    "In position manager solutions, coupling the CLB with a serial port creates solutions for EnDat2.2, bidirectional/serial/synchronous (BiSS), Tamagawa T-format and other serial encoder standards. The CLB on the F28004x has enough capability to implement two channels of most protocols."

  • Hi,

    As I said earlier - library is developed for single encoder use only.
    From the hardware standpoint - it depends on the encoder in use and the CLB resources used for the encoder implementation. 
    So, for instance it'll not be possible to implement 2 EnDat22 encoders but it'll be possible to implement 2 Tformat encoders, or 1 BiSS_C + 1 T-format etc.
    Also, though there is theoretical possibility of multiple encoders, since the current usage is enabled only via libraries - you can only support one.
    When the CLB tool is released later this month, you can design your own encoder interface with the CLB and validate multi-encoder feasibility as well.

  • Thanks a lot for the detailed information!

  • I've mostly dealt with ecoders with simple one way SPI interface. For this, the following schematics should show the approach:

    With the couple of Biss and EnDat encoders I've dealt with, I used SPI module directly without CLB (this was 10 years ago). It turns out that the most important feature of CLB is clock delay compensation. If you had MCU with McBSP port you could use it and generate delayed clock via external RC circuitry. You could even set delay programably via GPIO swithcable parallel capacitors. Now if you reduce the clock frequency, then you can do without clock delay compensation. In some cases you can even push the clock frequency and you can change clock polarity and clock phase settings in SPI in order to sample data in the right moments. But this is more of a hack suitable for prototyping, and I'd not recommend it for production.

    Now if you can live without clock delay compensation you can use just the SPI without CLB for Biss or EnDat communication if you want to have read/write acces, you'd need to expand the shown schematics with additional transceiver for MOSI signal. But I've always managed to use only one way communication with Biss and EnDat. Maybe I just had luck with the encoders, as they were configured correctly out of the box and they did not need any write access in order to work.

  • Thanks a lot for describing your approach and experiences from past projects!

    Sadly your attached schematic isn't visible. Would be cool if you can find a minute and try to post it again.

  • Here I go again.

    You do not actually need 2 GPIO. One is enough but you need external inverter to generate the other enable signal.

  • Thank you!