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TMS320F280049: SPI SOMI Delay time too long

User1164857
Intellectual 380 points

Part Number: TMS320F280049

Hello,

I work with the F280049 and come across a strange behaviour. Due to unexpected problems during SPI communication I looked a little closer into the timings of all signals.

I am using INTOSC2 which gives me a SYSCLK of around 96.25 Mhz as stated in the appropriate Technical Reference (SPRUI33B) on page 108. On my self designed board I have the recommended set of capacitors close to the chip and soldered everything by hand. So far I can tell, everything is connected fine and all solder points look good. All connections are tested with a multi meter.

My LSPCLKDIV = 0 so my peripheral clock should run wit system clock. The spi is configured as slave and my SPI clock is 10 Mhz, polarity is 0 and phase is 1. High speed mode is enabled as well as fifo. The datasheet (SPRS945D) tells me that the delay td(SOMI)S between the falling edge and a valid SPISOMI is 14 ns at max. But as far as I can't tell my oscilloscope shows me 19ns to 29ns jitter for the firs falling edge. The setup time for the SPI between SPISTE down and CLK up is 66ns. All edges look good and with small rise and fall times.

The SOMI pin is connected to a SN65LVDS2DBVR. CLK anf SIMO ar comming from a SN65LVDS1DBVR and have a 4 to 5 ns delay.

Can someone explain to me where this jitter and extra time is coming from? Any idea how to fix this?

Regards,
Martin

The picture shows the maximum delay (5ns from CLK + 29 ns from SOMI delay)

1 - SPISTE at Master

Ch2 - SOMI at Slave

9 - SIMO at Master

10 - CLK at Master

  • 0
    TI__Guru 55700 points

    Martin,

    I will check with the design team to double check on this number. But, it is highly unlikely that his number is incorrect.

    Have you tried connecting your SPI Master (FPGA) directly with F280049.SPI? If so, what was the number observed?

    Regards,

    Manoj

  • 0 in reply to Manoj Santha Mohan
    Intellectual 380 points

    Hello Manoj,

    the direct connection would cause a lot of work, so I will avoid it, until it seems to solve the problem. By now, the LVDS driver and LVDS receiver show their data sheet value delay times.

    I have another prototype board with the same layout and parts. It shows the same extended delay of SOMI. So it is either a hardware problem or a software problem. Could I change the delay value by a GPIO configuration or something like that? The correct rise and fall times indicate to me, that the capacitance and resistances at the chip are sufficient.

    The extended delay applies to rising edges as well as falling edges throughout the message.

    Regards,
    Martin

  • 0 in reply to User1164857
    TI__Guru 55700 points

    Martin,

    Are you making sure all your SPI pins are configured with GPIO Input qualfication "ASYNC"? If you have configured your SPI pins in other GPIO Input Qualification mode, then the delay you are seeing should be from synchronization delay introduced by GPIO Input Qualification.

    Regards,

    Manoj

  • 0 in reply to Manoj Santha Mohan
    Intellectual 380 points

    Hello Manoj,

    ASYNC Mode for appropriate GPIOS worked. Now the delay matches the data sheet value.

    Thank you very much.

    Regards,

    Martin