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TMS320F28030: SPI Rx buffer overrun flag

jw
Expert 1190 points
Part Number: TMS320F28030


Hello, in the case where the received  buffer overrun bit is set , what should the firmware do to manage the situation.

The sample code, clears the bit (SpiaRegs.SPIFFRX.bit.RXFFOVFCLR=1) but does not indicate steps to recover.

thanks

  • 0
    TI__Guru 54195 points

    The steps to recover need to be defined as part of your system--it's not something specific to the F28030. What kind of device are you communicating with? Fo example, maybe you need to reset the FIFO and send a message to the other device to request that it tries to send the missed data again?

    Whitney

  • 0 in reply to Whitney Dewey
    Expert 1190 points

    the communication path is 1/2 duplex  with F28030 being the slave.  A 2nd micro is the master which sends 16bit data to the slave at 500 times a second.. 

    the problem occurs when the master is powered cycled, I observed that data from the SpiaRegs.SPIRXBUF is corrupted and remains so, Power cycling  the slave fixes the problem.  The problem might be due to past data which is mixed with present data,  therefore flushing SPIRXBUF may help or possibly reset the  clock count after every packet to keeping the data and clock in sync

    SPIRXBUF  is read only, can you suggest anther method to clear this register

    Under normal conditions  the communication is very robust.

  • 0 in reply to jw
    TI__Guru 54195 points

    Have you tried just doing resets at the SPI level instead of doing a full power cycle? Like you could see if resetting the FIFOs works (see SPIFFTX.SPIRST, SPIFFTX.TXFIFO, SPIFFRX.RXFIFORESET), or if doing it at the FIFO level doesn't work, try a general software reset of the SPI as well (see SPICCR.SPISWRESET).

    Whitney

  • 0 in reply to Whitney Dewey
    Expert 1190 points

    hello Whitney, the SpiaRegs.SPIRXBUF is read directly.  After each read,  I rewrite the SPI/FIFO registers (identical to when the processor is powered on) which helped quite a bit. Can you suggest a reason why this is the case?

    Setting SPICCR.SPISWRESET = 0 had no effect, I'll try resetting the FIFO only and will let you know the results

     

  • 0 in reply to jw
    TI__Guru 54195 points

    It sounds like whatever is happening on the SPI signals when the master device is power cycled is confusing the F2803x SPI. You would have to look at them on a logic analyzer or something to see what exactly is happening--partially completed transmission, unexpected pin transitions, etc...

    Whitney