TMS320F280049: CRC-32 reflected by using VCU0

//###########################################################################
//
// FILE:   cpu_Timers_cpu01.c
//
// TITLE:  Cpu Timers Example for F2837xD.
//
//! \addtogroup cpu01_example_list
//! <h1> CPU Timers </h1>
//!
//! This example configures CPU Timer0, 1, and 2 and increments
//! a counter each time the timer asserts an interrupt.
//!
//! \b Watch \b Variables \n
//! - CpuTimer0.InterruptCount
//! - CpuTimer1.InterruptCount
//! - CpuTimer2.InterruptCount
//!
//
//###########################################################################
// $TI Release: F2837xD Support Library v3.06.00.00 $
// $Release Date: Mon May 27 06:48:24 CDT 2019 $
// $Copyright:
// Copyright (C) 2013-2019 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################

//
// Included Files
//
#include "F28x_Project.h"

//
// Function Prototypes
//
__interrupt void cpu_timer0_isr(void);
__interrupt void cpu_timer1_isr(void);
__interrupt void cpu_timer2_isr(void);
void CRC32_ADCCP_01(unsigned int *CRCResult, unsigned int  *CRCData, unsigned int   CRCLen);
void CRC32_ADCCP_02(unsigned int *CRCResult, unsigned int  *CRCData, unsigned int   CRCLen);

// Test data
unsigned int CRC_Test_01[16] = {0xFE,0x12,0x00,0x09,0x01,0x03,0x04,0x00,0x01,0x00,0x00,0xAB,0xF3,0x00,0x00,0x00};
unsigned int CRC_Test_02[16] = {0x7F,0x48,0x00,0x90,0x80,0xC0,0x20,0x00,0x80,0x00,0x00,0xD5,0xCF,0x00,0x00,0x00};  //flip data

//result put after pattern[16] 4 bytes
//CRC32_MODBUS(&CRC_Test[16], &CRC_Test[0], 16);
Uint16  test_CRC[20];
Uint32 CRC32_result01=0,CRC32_result02=0;

void main(void)
{
//
// Step 1. Initialize System Control:
// PLL, WatchDog, enable Peripheral Clocks
// This example function is found in the F2837xD_SysCtrl.c file.
//
    InitSysCtrl();

//
// Step 2. Initialize GPIO:
// This example function is found in the F2837xD_Gpio.c file and
// illustrates how to set the GPIO to it's default state.
//
    InitGpio();
    GPIO_SetupPinMux(65, GPIO_MUX_CPU1, 0);
    GPIO_SetupPinOptions(65, GPIO_OUTPUT, GPIO_PUSHPULL);

//
// Step 3. Clear all interrupts and initialize PIE vector table:
// Disable CPU interrupts
//
    DINT;

//
// Initialize the PIE control registers to their default state.
// The default state is all PIE interrupts disabled and flags
// are cleared.
// This function is found in the F2837xD_PieCtrl.c file.
//
    InitPieCtrl();

//
// Disable CPU interrupts and clear all CPU interrupt flags:
//
    IER = 0x0000;
    IFR = 0x0000;

//
// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
// This will populate the entire table, even if the interrupt
// is not used in this example.  This is useful for debug purposes.
// The shell ISR routines are found in F2837xD_DefaultIsr.c.
// This function is found in F2837xD_PieVect.c.
//
    InitPieVectTable();

//
// Interrupts that are used in this example are re-mapped to
// ISR functions found within this file.
//
    EALLOW;  // This is needed to write to EALLOW protected registers
    PieVectTable.TIMER0_INT = &cpu_timer0_isr;
    PieVectTable.TIMER1_INT = &cpu_timer1_isr;
    PieVectTable.TIMER2_INT = &cpu_timer2_isr;
    EDIS;    // This is needed to disable write to EALLOW protected registers

//
// Step 4. Initialize the Device Peripheral. This function can be
//         found in F2837xD_CpuTimers.c
//
    InitCpuTimers();   // For this example, only initialize the Cpu Timers

//
// Configure CPU-Timer 0, 1, and 2 to interrupt every second:
// 200MHz CPU Freq, 1 second Period (in uSeconds)
//
    ConfigCpuTimer(&CpuTimer0, 200, 1000000);
    ConfigCpuTimer(&CpuTimer1, 200, 1000000);
    ConfigCpuTimer(&CpuTimer2, 200, 1000000);

//
// To ensure precise timing, use write-only instructions to write to the
// entire register. Therefore, if any of the configuration bits are changed in
// ConfigCpuTimer and InitCpuTimers (in F2837xD_cputimervars.h), the below
// settings must also be updated.
//
    CpuTimer0Regs.TCR.all = 0x4000;
    CpuTimer1Regs.TCR.all = 0x4000;
    CpuTimer2Regs.TCR.all = 0x4000;

//
// Step 5. User specific code, enable interrupts:
//

//
// Enable CPU int1 which is connected to CPU-Timer 0, CPU int13
// which is connected to CPU-Timer 1, and CPU int 14, which is connected
// to CPU-Timer 2:
//
    IER |= M_INT1;
    IER |= M_INT13;
    IER |= M_INT14;

//
// Enable TINT0 in the PIE: Group 1 interrupt 7
//
    PieCtrlRegs.PIEIER1.bit.INTx7 = 1;

//
// Enable global Interrupts and higher priority real-time debug events:
//
//    EINT;  // Enable Global interrupt INTM
    ERTM;  // Enable Global realtime interrupt DBGM

//
// Step 6. IDLE loop. Just sit and loop forever (optional):
//
    test_CRC[0]=1;
    test_CRC[1]=2;
//    CRC_Test[0]=0xFE;
    CRC32_ADCCP_01(&CRC_Test_01[16], &CRC_Test_01[0], 16);  //result 0x70F15A61
    CRC32_ADCCP_02(&CRC_Test_02[16], &CRC_Test_02[0], 16);  //result


    while(1)
    {

    }
}

//
// cpu_timer0_isr - CPU Timer0 ISR with interrupt counter
//
__interrupt void cpu_timer0_isr(void)
{
   CpuTimer0.InterruptCount++;

   //
   // Acknowledge this interrupt to receive more interrupts from group 1
   //
   PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
}

//
// cpu_timer1_isr - CPU Timer1 ISR
//
__interrupt void cpu_timer1_isr(void)
{
   CpuTimer1.InterruptCount++;
   asm("    NOP"); //1
   asm("    NOP"); //2
   asm("    NOP"); //3
   asm("    NOP"); //4
   asm("    NOP"); //5
   asm("    NOP"); //6
}

//
// cpu_timer2_isr CPU Timer2 ISR
//
__interrupt void cpu_timer2_isr(void)
{
   CpuTimer2.InterruptCount++;
}


void CRC32_ADCCP_01(unsigned int *CRCResult, unsigned int  *CRCData, unsigned int   CRCLen)
{             //                *XAR4:CRCResult           XAR5 :CRCData            AL:CRCLen
    asm("    MOV AL,#16              ; AL = CRCLen, buffer to AR7");
    asm("    MOV AR7,AL              ; AL = CRCLen, buffer to AR7");
    asm("    MOVB ACC, #0            ; Init CRCResult            ");
    asm("    SUBB ACC, #1            ; Set to be 0xFFFFFFFF      ");
    asm("    MOVL *XAR4,ACC          ; *CRCResult = 0xFFFFFFFF   ");
    asm("    VMOV32 VCRC, *XAR4      ; Set VCRC = 0xFFFFFFFF     ");

    asm("    MOV AL, AR7             ; Restore AL = CRCLen");
    asm("    LSR AL, #2              ; AL = CRCLen/4      ");
    asm("    SUBB AL, #1             ; AL = AL - 1        ");
    asm("    VSETCRCMSGFLIP                               ");
    asm("    NOP                     ; Align RPTB to an odd address");
//    asm("    NOP                     ; Align RPTB to an odd address");
//    asm(".align     (2)                     ; Align RPTB to an odd address");
    asm("    RPTB CRC32MBS_done, AL   ; Execute block of code AL + 1 times");
    asm("    VCRC32L_1 *XAR5++       ; Calculate CRC for 4 bytes         ");
    asm("    VCRC32L_1 *XAR5++       ; ...");
    asm("    VCRC32L_1 *XAR5++       ; ...");
    asm("    VCRC32L_1 *XAR5++       ; ...");
    asm("CRC32MBS_done: ");

    asm("    VCLRCRCMSGFLIP                               ");
    asm("    VMOV32 ACC, VCRC        ; Store the result   ");
    asm("    FLIP AL                 ; Relect final result");
    asm("    FLIP AH                                      ");
    asm("    XOR AL, #0xffff         ; XOR to 0xFFFFFFFF  ");
    asm("    XOR AH, #0xffff");

    asm("    MOV DP,#_CRC32_result01            ; get DP");
    asm("    MOVW @_CRC32_result01, AH          ; byte switch");
    asm("    MOVW @_CRC32_result01+1, AL        ; ");


    asm("    LRETR                       ; return to caller");
}

void CRC32_ADCCP_02(unsigned int *CRCResult, unsigned int  *CRCData, unsigned int   CRCLen)
{             //                *XAR4:CRCResult           XAR5 :CRCData            AL:CRCLen
    asm("    MOV AL,#16              ; AL = CRCLen, buffer to AR7");
    asm("    MOV AR7,AL              ; AL = CRCLen, buffer to AR7");
    asm("    MOVB ACC, #0            ; Init CRCResult            ");
    asm("    SUBB ACC, #1            ; Set to be 0xFFFFFFFF      ");
    asm("    MOVL *XAR4,ACC          ; *CRCResult = 0xFFFFFFFF   ");
    asm("    VMOV32 VCRC, *XAR4      ; Set VCRC = 0xFFFFFFFF     ");

    asm("    MOV AL, AR7             ; Restore AL = CRCLen");
    asm("    LSR AL, #2              ; AL = CRCLen/4      ");
    asm("    SUBB AL, #1             ; AL = AL - 1        ");
//    asm("    VSETCRCMSGFLIP                               ");
    asm("    NOP                     ; Align RPTB to an odd address");
    asm("    NOP                     ; Align RPTB to an odd address");
//    asm(".align     (2)                     ; Align RPTB to an odd address");
    asm("    RPTB CRC32MBS_done2, AL   ; Execute block of code AL + 1 times");
    asm("    VCRC32L_1 *XAR5++       ; Calculate CRC for 4 bytes         ");
    asm("    VCRC32L_1 *XAR5++       ; ...");
    asm("    VCRC32L_1 *XAR5++       ; ...");
    asm("    VCRC32L_1 *XAR5++       ; ...");
    asm("CRC32MBS_done2: ");

//    asm("    VCLRCRCMSGFLIP                               ");
    asm("    VMOV32 ACC, VCRC        ; Store the result   ");
    asm("    FLIP AL                 ; Relect final result");
    asm("    FLIP AH                                      ");
    asm("    XOR AL, #0xffff         ; XOR to 0xFFFFFFFF  ");
    asm("    XOR AH, #0xffff");

    asm("    MOV DP,#_CRC32_result02            ; get DP");
    asm("    MOVW @_CRC32_result02, AH          ; byte switch");
    asm("    MOVW @_CRC32_result02+1, AL        ; ");

    asm("    LRETR                       ; return to caller");
}


//
// End of file
//