Hello
After make working the Biss library without any problem, I'm facing problem with the EnDat.
From the exemple code, the data receive during the delay compensation are bad due to the CRC check.
I comment the "ESTOP0" instruction to continue.
Then I receive Data position, but CRC is bad also always.
Then, I read the SPI signal.
CH1 Yellow: GPIO 6 EnDat Sensor Clock
CH2: Blue: GPIO 7 SPI Slave Clock
CH3: GPIO 34 ENDAT_DIR
CH4: Green: SPISIMO = ENDAT_DIN
I read the SPI config register, POLARITY = 1, and CLKPHASE = 0. Then this means "Falling edge without delay" So input data are sampled on SPI Clk rising edge, when EnDatSensor update data on th rising edge of its clock.
But according the scope, the rising edge of SPI is near to the rising edge of the Sensor.. I think SPI input some time bad sample because Rising edge come to fast?
Receive SPI Data for the scope above is : 0x0031, 0x872C, 0xA497. Some word are Ok, but some are bad where on SPI Data, I thing read: 0x0031 A69C 1D24
Calculated compensation delay (even if CRC bad) is 13.
SPI clock always let to 200KHz (not change to 8MHz... but same problem at 8MHz)
sensor is Heidenhain EQI1331
Thank




