Part Number: TMS320F28379D
This refers to the use of two SRAM devices (CY62167EV30) connected to the same EMIF module, controlled by two CPU's as shown below:
We are trying to get CPU2 to write to a sram (CS3) variable. But currently the CPU1 has write access to SRAM it is writing to variable in CS2 range.
On cpu2 we have to have the following code.
Uint16_t uwTest2; compiler allocates this at 0x300040 which is in CS3 range of EMIF1 controller.
/** - Grab EMIF1 for CPU2. */
while(Emif1ConfigRegs.EMIF1MSEL.all != 0x2)
{
Emif1ConfigRegs.EMIF1MSEL.all = 0x93A5CE72;
}
/** - cpu2 now has write access to EMIF1. */
uwTest2 = 7;
/** - cpu2 release access to EMIF1. */
Emif1ConfigRegs.EMIF1MSEL.all = 0x93A5CE70;
To summarize: CPU1 uses first SRAM located at CS2 (0x100000). CPU2 uses second SRAM located at CS3 (0x300000).
Please we are not interested in paging on CS2 two SRAMS at 0x100000 – 0x300000.
I cannot see any examples showing two cores trying to access two different srams on the same EMIF1 controller.
Thank you!
