Compiler/TMS320F28069M: .bin file contents

/*
//###########################################################################
//
// FILE:    F28069.cmd
//
// TITLE:   Linker Command File For F28069 Device
//
//###########################################################################
// $TI Release: F2806x C/C++ Header Files and Peripheral Examples V135 $
// $Release Date: Sep 8, 2012 $
//###########################################################################
*/

/* ======================================================
// For Code Composer Studio V2.2 and later
// ---------------------------------------
// In addition to this memory linker command file,
// add the header linker command file directly to the project.
// The header linker command file is required to link the
// peripheral structures to the proper locations within
// the memory map.
//
// The header linker files are found in <base>\F2806x_headers\cmd
//
// For BIOS applications add:      F2806x_Headers_BIOS.cmd
// For nonBIOS applications add:   F2806x_Headers_nonBIOS.cmd
========================================================= */

/* ======================================================
// For Code Composer Studio prior to V2.2
// --------------------------------------
// 1) Use one of the following -l statements to include the
// header linker command file in the project. The header linker
// file is required to link the peripheral structures to the proper
// locations within the memory map                                    */

/* Uncomment this line to include file only for non-BIOS applications */
/* -l F2806x_Headers_nonBIOS.cmd */

/* Uncomment this line to include file only for BIOS applications */
/* -l F2806x_Headers_BIOS.cmd */

/* 2) In your project add the path to <base>\F2806x_headers\cmd to the
   library search path under project->build options, linker tab,
   library search path (-i).
/*========================================================= */

/* Define the memory block start/length for the F2806x
   PAGE 0 will be used to organize program sections
   PAGE 1 will be used to organize data sections

   Notes:
         Memory blocks on F28069 are uniform (ie same
         physical memory) in both PAGE 0 and PAGE 1.
         That is the same memory region should not be
         defined for both PAGE 0 and PAGE 1.
         Doing so will result in corruption of program
         and/or data.

         Contiguous SARAM memory blocks can be combined
         if required to create a larger memory block.
*/

MEMORY
{
PAGE 0 :   /* Program Memory */
           /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */
   OTP         : origin = 0x3D7800, length = 0x000400     /* on-chip OTP */
   BL_FH       : origin = 0x3D8000, length = 0x004000     /* on-chip FLASH for bootloader*/
   CRC         : origin = 0x3DC000, length = 0x000100
   APP_FLASH   : origin = 0x3DC100, length = 0x01BE80     /* on-chip FLASH for application*/
   CSM_RSVD    : origin = 0x3F7F80, length = 0x000076     /* Part of FLASHA.  Program with all 0x0000 when CSM is in use. */
   BEGIN       : origin = 0x3F7FF6, length = 0x000002     /* Part of FLASHA.  Used for "boot to Flash" bootloader mode. */
   CSM_PWL_P0  : origin = 0x3F7FF8, length = 0x000008     /* Part of FLASHA.  CSM password locations in FLASHA */

   FPUTABLES   : origin = 0x3FD590, length = 0x0006A0	 /* FPU Tables in Boot ROM */
   IQTABLES    : origin = 0x3FDC30, length = 0x000B50    /* IQ Math Tables in Boot ROM */
   IQTABLES2   : origin = 0x3FE780, length = 0x00008C    /* IQ Math Tables in Boot ROM */
   IQTABLES3   : origin = 0x3FE80C, length = 0x0000AA	 /* IQ Math Tables in Boot ROM */

   ROM         : origin = 0x3FF3B0, length = 0x000C10     /* Boot ROM */
   RESET       : origin = 0x3FFFC0, length = 0x000002     /* part of boot ROM  */
   VECTORS     : origin = 0x3FFFC2, length = 0x00003E     /* part of boot ROM  */

PAGE 1 :   /* Data Memory */
           /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */
           /* Registers remain on PAGE1                                                  */

   BOOT_RSVD   : origin = 0x000000, length = 0x000050     /* Part of M0, BOOT rom will use this for stack */
   PIEVECT     : origin = 0xD00,    length = 0x100
   RAMM0_1     : origin = 0x000050, length = 0x0007B0     /* on-chip RAM block M0 */
   RAM_FUNCS   : origin = 0x008000, length = 0x002100
   RAM         : origin = 0x00a100, length = 0x007F00     /* on-chip RAM */
   USB_RAM     : origin = 0x040000, length = 0x000800     /* USB RAM		  */
}

/* Allocate sections to memory blocks.
   Note:
         codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code
                   execution when booting to flash
         ramfuncs  user defined section to store functions that will be copied from Flash into RAM
*/


SECTIONS
{
   bl_table            : > 0x3D8000,   PAGE = 0, type = DSECT
   app_table           : > CRC,   PAGE = 0

   /* Allocate program areas: */
   .TI.ramfunc         : {} LOAD=APP_FLASH PAGE = 0,
                            RUN=RAM_FUNCS    PAGE = 1,
                            crc_table(_CRCTestVector),
                            TABLE(BINIT)


   /* Allocate program areas: */
   GROUP               : > APP_FLASH,     PAGE = 0, crc_table(_CRCTestVector)
   {
       .cinit
       .pinit
       .binit
       codestart
       .text
       /* Initalized sections to go in Flash */
       /* For SDFlash to program these, they must be allocated to page 0 */
       .econst
       .switch
   }


   .TI.crctab          : > CRC
   csmpasswds          : > CSM_PWL_P0, PAGE = 0
   csm_rsvd            : > CSM_RSVD,   PAGE = 0
   //.cinit              : > APP_FLASH,           PAGE = 0
   //.binit              : {} > APP_FLASH,        PAGE = 0
   //.pinit              : > APP_FLASH,           PAGE = 0
   //.text               : > APP_FLASH,           PAGE = 0
   //codestart           : > BEGIN,           PAGE = 0
   //.TI.ramfunc         : {} LOAD=APP_FLASH      PAGE = 0,
                           // RUN=RAM_FUNCS   PAGE = 1,
                           // TABLE(BINIT)
   csmpasswds          : > CSM_PWL_P0,      PAGE = 0
   csm_rsvd            : > CSM_RSVD,        PAGE = 0

   /* Allocate uninitalized data sections: */
   .stack              : > RAM,              PAGE = 1
   // Give ebss more RAM(task stacks)
   .ebss               : > RAM | RAMM0_1,    PAGE = 1
   .esysmem            : > RAM,              PAGE = 1
   // .cio buf is used by OS no real way around it
   .cio                : > RAMM0_1,          PAGE = 1


   /* Allocate IQ math areas: */
   IQmath              : > APP_FLASH,   PAGE = 0            /* Math Code */
   IQmathTables        : > IQTABLES,     PAGE = 0, TYPE = NOLOAD

   /* Allocate FPU math areas: */
   FPUmathTables       : > FPUTABLES,  PAGE = 0, TYPE = NOLOAD

  /* Uncomment the section below if calling the IQNexp() or IQexp()
      functions from the IQMath.lib library in order to utilize the
      relevant IQ Math table in Boot ROM (This saves space and Boot ROM
      is 1 wait-state). If this section is not uncommented, IQmathTables2
      will be loaded into other memory (SARAM, Flash, etc.) and will take
      up space, but 0 wait-state is possible.
   */
	/*
   IQmathTables2    : > IQTABLES2, PAGE = 0, TYPE = NOLOAD
   {

              IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)

   }
	*/
   /* Uncomment the section below if calling the IQNasin() or IQasin()
      functions from the IQMath.lib library in order to utilize the
      relevant IQ Math table in Boot ROM (This saves space and Boot ROM
      is 1 wait-state). If this section is not uncommented, IQmathTables2
      will be loaded into other memory (SARAM, Flash, etc.) and will take
      up space, but 0 wait-state is possible.
   */
   /*
   IQmathTables3    : > IQTABLES3, PAGE = 0, TYPE = NOLOAD
   {

              IQmath.lib<IQNasinTable.obj> (IQmathTablesRam)

   }
   */

   /* .reset is a standard section used by the compiler.  It contains the */
   /* the address of the start of _c_int00 for C Code.   /*
   /* When using the boot ROM this section and the CPU vector */
   /* table is not needed.  Thus the default type is set here to  */
   /* DSECT  */
   .reset              : > RESET,      PAGE = 0, TYPE = DSECT
   vectors             : > VECTORS,    PAGE = 0, TYPE = DSECT

}

/*
//===========================================================================
// End of file.
//===========================================================================
*/