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F28335 GPIO pull-up state during reset

Bret
Expert 4865 points

Champs,

I have a customer asking about the state of GPIO pullups while reset is asserted and after reset has been released.  Looking at the wiki and the System Control and Interrupts guide, I'm not sure.  All of the GPIO mux diagrams in the guide show pullups being disabled when XRS is low and disabled after reset  (left-hand side of diagram).  However, the wiki states that pins that can _not_ be used as PWM will have pull-ups _enabled_ at reset and then must be disable by software after reset.

Any clarification you could provide would be appreciated.

Thanks,

Bret

  • 0
    TI__Guru* 90955 points

    Bret Felton said:
    Looking at the wiki and the System Control and Interrupts guide, I'm not sure.  All of the GPIO mux diagrams in the guide show pullups being disabled when XRS is low and disabled after reset  (left-hand side of diagram).  However, the wiki states that pins that can _not_ be used as PWM will have pull-ups _enabled_ at reset and then must be disable by software after reset.

    Bret,

    I agree the MUX diagrams are confusing and need to be changed to be clear.

    Refer the customer to the Pullup disable registers in the system control guide www.ti.com/lit/SPRUFB0 (i.e. Figure 62. GPIO Port A Pullup Disable (GPAPUD) Registers, Figure 63, and Figure 64).  The reset value of "1" means the pullup is disabled on reset.  A "0" means it is not disabled.

    Only GPIO pins that correspond to ePWM outputs have a "1" meaning they are disabled on reset. (GPIO0-GPIO11)

     

    -Lori