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Hi,
I am doing 1: 2 communication using McBSP of TMS320F28335.
The communication connection diagram is as follows.
By the way, There is a problem with the master's FSR signal.
#1). If only Slave1 is connected to the Master, the voltage of 3V is normally checked. - Communication is normal.
#2). If Slave1 and Slave2 are connected to Master together, the voltage drops to 3V --> 2V. - Intermittent error occurs in communication.
Please give me the hints about the cause of the problem.
Thank you for your interest in my question.
Nam,
Thanks for reaching out to the E2E forum. Can you specify which GPIO pin you are bringing the FSR signal to? Most GPIO pins have a maximum drive strength of 4mA, but there are a few that are 8mA.
From your question I assume you are using the F28335 to generated the frame sync vs an external sync.
There would be only a couple of reasons to see a mid-level voltage on a digital output:
1)There is load in excess of the drive strength I mentioned earlier; you may want to see if the slaves have any sort of pull down resistors that could be consuming extra current or if there are any external PDs on the net.
2)There is contention on the bus, i.e. one of the slaves is driving against the F28335. You mention that when Slave 2 is added to Slave 1 the issue appears. Can you try to just have slave 2 on the bus and see if alone it is OK?
Look forward to your thoughts and feedback.
Best,
Matthew
Nam,
Checking back to see if you have had a chance to relook at your system for the above.
Best regards,
Matthew
There is no problem in the sole connection between the Slave2 device and the Master.
I'll check out the other solutions you talked to me.
Thank you.
Nam,
Just checking back to see if you still require assistance on the above issue.
Best,
Matthew
Matthew,
I'm considering applying the digital buffer to signal line design.
If I have additional issues with my design, I will post a additional post.
Thank you for your interest.
Thank you.