Other Parts Discussed in Thread: C2000WARE
I need to sequentially sample all the sixteen analog inputs with the ADC. Therefore I've set the sequential sampling mode (SMODE_SEL=0) and the cascaded mode (SEQ_CASC=1).
Apart from that, I'm using the same configuration described in the first example in the table 1-7 of SPRU812A: SYSCLKOUT=150 MHz, HSPCP=3, ADCLKPS=0, CPS=0, ACQ_PS=0. In this configuration I'm expecting to get the conversion time of table 1-7 (12.5 MSPS or 80 ns) and therefore I'm expecting that for all of the sixteen channels, the whole conversion will take 80*16=1280 ns.
Instead, measuring the time between SOC (interrupt triggered by EPWM) and EOC (interrupt triggered by ADC), I get 1920 ns. Apparently each conversion takes three ADC clocks instead of two.
This is also confirmed by increasing ACQ_PS: each time the sampling takes one additional ADC clock:
| ACQ_PS | t calculated | t measured |
| 0 | 1280 | 1920 |
| 1 | 1920 | 2580 |
| 2 | 2560 | 3220 |
By reading SPRU812A, it seems that this behavior is correct for the simultaneous sampling mode (SMODE_SEL=1) where obviously two ADC clocks are needed in order to convert two channels (see Figure 1-3). But I'm in the sequential sampling mode, where just one ADC clock should be needed for the conversion (see Figure 1-2).
What am I doing wrong?
Thank you!
L.
