TMS320F28375D: SRAM vs SDRAM - performance and tradeoffs

Lenio Cacula said:

i. I discussed with our SW team, and it sounds like we may have some random in our RAM access in addition to the block transfers graphed
Note: I understand from the Accessing External SDRAM document that there are some performance penalties, but it would be good to understand these penalties better.

Can you point to specific reference(s) of performance penalties in the document(s) that require clarification?  I don't mind elaborating, but I am not sure which aspect is of concern.

Lenio Cacula said:

1. Can you get a time for what a single 16 bit word access is for ASRAM vs SDRAM? We can assume the same chip used as the example from the TRM.

The bus activity time for a single word is derived directly from the EMIF configuration registers.  The EMIF is the controller where all activity is generated relative to the EMIF peripheral clock.  The only additional latency would be the 3-cycle synchronization latency described in the appnote.

Lenio Cacula said:

2. Are there graphs for the 1-512 transfers?

No, the measurement error becomes proportionately greater for smaller transfer sizes so it makes more sense to hand-calculate the bit-rate based on the EMIF settings.

Lenio Cacula said:

b. Does TI have a ‘clean’ reference design that was used for the throughput metrics? (note that the design referenced has a number of caveats / limitations as a result of the 60 pin connector)

Yes, there are caveats to the reference design, but it operates at full speed and demonstrates functionality beyond what would typically be implemented in a system.  The reference design was the platform used for collecting the throughput benchmarks.

Lenio Cacula said:

c. Do you have a pretty good sense for the timing associated with the SDRAM datasheets?

The EMIF configuration tool can be useful.

Lenio Cacula said:

i. With a 5nS EMIF clock, is the effective fastest we can run this at = 10nS / transfer?

The EMIF will typically be the speed-limiting factor for SDRAMs manufactured today.  In otherwords, modern SDRAMs support faster operation than the EMIF.

Lenio Cacula said:

d. Are there performance penalties for using a 32 bit wide bus (word manipulations -> read / modify / write operations on 16 bit variables)

The EMIF can perform single byte accesses.  There are no inherent cycle penalties for standalone 16b operations.  32b operations would obviously be the most efficient use of system resources.

Lenio Cacula said:

e. Does the memory access look like any other memory access from an machine code perspective, but just that there are wait states injected as the correct memory location is configured to be read from?

Correct, it behaves like any other memory mapped space with the exception of FAR accesses in the SDRAM space.

Lenio Cacula said:

2. Layout Rules - Does TI have recommendations regarding HS layout for these interfaces?

Industry best practices are generally sufficient for these speeds.

Lenio Cacula said:

a. Is series termination recommended?

Series termination can be used, but they are not a requirement.  The reference design does not include termination.

Lenio Cacula said:

b. Do the memory pins have slew rate / drive strength settings?

There are no configurable settings.

Lenio Cacula said:

c. At these speeds, what are the recommendations for length matching?

Length matching is a good idea.  The proper way to determine targets for matching would be to compare the PCB signal skew versus the setup and hold timing requirements between the EMIF and external memory.  I think they will find that the timing budget is very relaxed when the memory is placed close to the EMIF.

Lenio Cacula said:

d. Controlled Impedance? 50 Ohm Single Ended?

Like length matching, this is a good idea, but is not required.  As with length matching, the importance of impedance control can be minimized with optimal placement.

Lenio Cacula said:

a. Are there possibilities for SDRAM stress testing? Can the interface support higher speeds?

This is up to the customer.  It would be reasonable to assume that all designs have performance margin, but TI can only support datasheet conditions.

Lenio Cacula said:

b. How does TI recommend evaluating the SDRAM interface for reliability & robustness?
i. SI Testing?
ii. How to check across environmental conditions?

We do not have any specific recommendations here.  I suppose it would be similar to validating a communications interface.  There are well-documented memory test patterns (like March) that can be implemented.

Lenio Cacula said:

c. Can you recommend an eval kit that would allow us to checkout some of the details related to integration of this technology?

The reference design is a good evaluation platform that works with the LaunchPad and controlCARD.

One additional note on below point -

Lenio Cacula

i. With a 5nS EMIF clock, is the effective fastest we can run this at = 10nS / transfer?

The EMIF will typically be the speed-limiting factor for SDRAMs manufactured today.  In otherwords, modern SDRAMs support faster operation than the EMIF.

For SDRAM, max EMIF frq supported is 100MHz, 10ns EMIF clock. Also in SDRAM there are some other overheads like CAS latency so one need to look at the throughput number.

Regards,

Vivek Singh