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TMS320F28379D: What is the recommended way to oversample a single channel synchronized to a single trigger ?

Bhawandeep Singh
Prodigy 160 points
Part Number: TMS320F28379D

Hi,

My design has two input signals - one is a synchronization digital input pulse and the second is an analog input being fed to the ADC.

When the synchronizing digital input makes a rising transition, I wish to take multiple (10-16) successive equi-distant/ equi-spaced samples of the the analog input channel.

Presently, one way to do is to have multiple SOCs (say 10), select the digital input as trigsel for each of them and have different ACQPS.

With a clock time period of 40ns and each SOC being successively 10 CC delayed - so SOC0 is after 10 CC from trigger, SOC1 is after 20 CC from trigger and so on, will the S+H timing for the ADC be met for each sample ?

If not, what is the recommended way to do it ?

Thanks and best regards

Bhawandeep Singh

 

  • 0
    TI__Mastermind 37680 points

    Hi Bhawandeep,

    Yes, best option is to use 10 SOCs.  S+H timing will remain unchanged regardless of the occurrence of the trigger.  There is a section in the TRM that discusses how to control the sequence of SOC conversions as soon as the trigger is present.  Please see section "ADC Conversion Priority" that discusses conversion sequencing in detail and it will be a good place to start.

    Best regads,

    Joseph

  • 0 in reply to Joseph Casuga
    Prodigy 160 points

    Hi Joseph,

    Thanks a lot for addressing and routing me to TRM.

    I have a question.

    I found the min. value of ACQPS for S+H to work correctly in 12 bit single ended mode  = 75ns.

    Also, In case the input signal has a steep slope during S+H, is the ADC output same in the two cases - 

    1. ACQPS = ACQPS(min) after trigger 

    2. ACQPS >  ACQPS(min) after trigger 

    I understand the two cases are expected to given same ADC output if the analog input does not change during ACQPS. 

    But I need to quantify what happens in cases when analog input is steeply changing during the ACQPS.

    In particular - in our design - the analog signal goes down from .5V to 0 in .8 us (and vice-versa).

    Will the ADC capacitance charge/ discharge fast enough and give same readings for the two cases -

    1 - Trigger is at the beginning of .8us window and ACQPS = .8us (given in number of cycles)

    2 - ACQPS = ACQPS(min) and Trigger is a software trigger at time .8us - ACQPS(min) after/ into the .8us window.

    Thanks and best regards

    Bhawandeep Singh

  • 0 in reply to Bhawandeep Singh
    TI__Mastermind 37680 points

    Hi Bhawandeep,

    Min S+H specified for 12B single ended is 75ns, but this may change depending on your external impedance.  There is also a section in the TRM ("Coosing an Acquisition Window Duration") that takes into account the internal impedance of the ADC (Ron, Ch, Cp which are available in the datasheet) and the external source impedances (Rs, Cs) that calculates the optimum ACQPS with the desired settling error.  You may want to just go through that as well just to make sure your application is using the correct ACQPS especially that you are sampling a high slew rate signal.

    ACQPS is the time (in SYSCLK cycles) that you allow the internal ADC sampling capacitor to close so that the input signal will charged for that duration, afterwhich the sampling capacitor disconnects from the input source.  The charge stored in the sampling capacitor will then be quantized by the SAR in the ADC module and upon completion (the number of SYSCLK cycles required to convert dependent on the prescaler used), the ADC module will give the digital output code.  You may also want to look at the ADC timing diagrams in both the TRM and datasheet as those will provide you the total time it takes to sample and convert the signal based upon the ADC parameter your application uses.  Sorry, i cannot give a direct answer to whether the ACQPS is enough for what you are intending to sample.  What i am emphasizing here is the importance of using the correct ACQPS value (which is based from external and internal impedances).  If ACQPS is not enough, then signal is not settle to the level you need and conversion results will be unreliable.  What i suggest is to first check if you have the correct ACQPS settings, then with the timing diagrams, check how long will each conversion take and see if it meets the sampling you desire for the high slew rate signal you are trying to convert.  If you have questions regarding the ADC timing, let me know.

    To your other question regarding cap charge/discharge, as soon as quantization is completed.  The sampling capacitor is fully discharged.

    Regards,

    Joseph