So what is the problem with initializing pwm ecap and external interrupts, no pwm is generated, on f28377s

/* global (called in other files) */
extern void int_rx_mnm1221_m(void);		/* use in INTRX interrupt */
extern short ctrl_mnm1221_m(void);		/* use in timer interrupt for NC */

__interrupt void xintrx_ISR(void)
{
	int_rx_mnm1221_m();
	PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
}
__interrupt void ecap3_ISR(void)
{
   ECap3Regs.ECCLR.bit.CEVT1 = 1;
   ECap3Regs.ECCLR.bit.CEVT2 = 1;
   ECap3Regs.ECCLR.bit.CEVT3 = 1;
   ECap3Regs.ECCLR.bit.CEVT4 = 1;
   ECap3Regs.ECCLR.bit.INT = 1;

   phase_monitor = ctrl_mnm1221_m ();

   // Acknowledge this interrupt to receive more interrupts from group 3
   PieCtrlRegs.PIEACK.all = PIEACK_GROUP4;
}

short monitor_phase (void)
{
	return phase_monitor;
}

static void InitEPwm5 (void)
{
	EALLOW;
	CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0;
	EDIS;

	EPwm5Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up
	EPwm5Regs.TBPRD = 37499;
	EPwm5Regs.TBPHS.all = 0x00000000;
	EPwm5Regs.AQCTLA.bit.PRD = AQ_TOGGLE;      // Toggle on PRD

	//
	// TBCLK = SYSCLKOUT
	//
	EPwm5Regs.TBCTL.bit.HSPCLKDIV = 1;
	EPwm5Regs.TBCTL.bit.CLKDIV = 0;

//	EPwm5TimerDirection = EPWM_TIMER_UP;

	EALLOW;
	CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1;
	EDIS;
}

static void InitECap3(void)
{
	ECap3Regs.ECEINT.all = 0x0000;          // Disable all capture __interrupts
	ECap3Regs.ECCLR.all = 0xFFFF;           // Clear all CAP __interrupt flags
	ECap3Regs.ECCTL1.bit.CAPLDEN = 0;       // Disable CAP1-CAP4 register loads
	ECap3Regs.ECCTL2.bit.TSCTRSTOP = 0;     // Make sure the counter is stopped

	//
	// Configure peripheral registers
	//
	ECap3Regs.ECCTL2.bit.CONT_ONESHT = 1;   // One-shot
	ECap3Regs.ECCTL2.bit.STOP_WRAP = 3;     // Stop at 4 events
	ECap3Regs.ECCTL1.bit.CAP1POL = 1;       // Falling edge
	ECap3Regs.ECCTL1.bit.CAP2POL = 0;       // Rising edge
	ECap3Regs.ECCTL1.bit.CAP3POL = 1;       // Falling edge
	ECap3Regs.ECCTL1.bit.CAP4POL = 0;       // Rising edge
	ECap3Regs.ECCTL1.bit.CTRRST1 = 1;       // Difference operation
	ECap3Regs.ECCTL1.bit.CTRRST2 = 1;       // Difference operation
	ECap3Regs.ECCTL1.bit.CTRRST3 = 1;       // Difference operation
	ECap3Regs.ECCTL1.bit.CTRRST4 = 1;       // Difference operation
	ECap3Regs.ECCTL2.bit.SYNCI_EN = 1;      // Enable sync in
	ECap3Regs.ECCTL2.bit.SYNCO_SEL = 0;     // Pass through
	ECap3Regs.ECCTL1.bit.CAPLDEN = 1;       // Enable capture units

	ECap3Regs.ECCTL2.bit.TSCTRSTOP = 1;     // Start Counter
	ECap3Regs.ECCTL2.bit.REARM = 1;         // arm one-shot
	ECap3Regs.ECCTL1.bit.CAPLDEN = 1;       // Enable CAP1-CAP4 register loads
	ECap3Regs.ECEINT.bit.CEVT4 = 1;         // 4 events = __interrupt
}

/// ----------------------------------------------------------------------------------
static void IoInit(void)
{
	EALLOW;

	GpioDataRegs.GPACLEAR.all		= 0x3900ul;	
//	GpioDataRegs.GPASET.bit.GPIO8	= 1;		
	GpioCtrlRegs.GPADIR.all			= 0xf980ul;	

	//DIR = GPIO16
	GpioCtrlRegs.GPAPUD.bit.GPIO16 = 0;
	GpioDataRegs.GPADAT.bit.GPIO16 = 0;
	GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 0;
	GpioCtrlRegs.GPADIR.bit.GPIO16 = 1;

	// nCSIO = GPIO17
	GpioCtrlRegs.GPAPUD.bit.GPIO17 = 0;
	GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 0;
	GpioDataRegs.GPADAT.bit.GPIO17 = 1;
	GpioCtrlRegs.GPADIR.bit.GPIO17 = 1;

	// cs0 = GPIO32
	GpioCtrlRegs.GPBPUD.bit.GPIO32 = 0;
	GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 0;
	GpioDataRegs.GPBDAT.bit.GPIO32 = 1;
	GpioCtrlRegs.GPBDIR.bit.GPIO32 = 1;

	// cs2 = GPIO34
	GpioCtrlRegs.GPBPUD.bit.GPIO34 = 0;
	GpioCtrlRegs.GPBMUX1.bit.GPIO34 = 0;
	GpioDataRegs.GPBDAT.bit.GPIO34 = 1;
	GpioCtrlRegs.GPBDIR.bit.GPIO34 = 1;

	// cs3 = GPIO35
	GpioCtrlRegs.GPBPUD.bit.GPIO35 = 0;
	GpioCtrlRegs.GPBMUX1.bit.GPIO35 = 0;
	GpioDataRegs.GPBDAT.bit.GPIO35 = 1;
	GpioCtrlRegs.GPBDIR.bit.GPIO35 = 1;

	// cs4 = GPIO28
	GpioCtrlRegs.GPAPUD.bit.GPIO28 = 0;
	GpioDataRegs.GPADAT.bit.GPIO28 = 0;
	GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 1;
	GpioCtrlRegs.GPADIR.bit.GPIO28 = 1;


	// nRESET = GPIO13
	// Enable an GPIO output on GPIO13, set it high
	GpioCtrlRegs.GPAPUD.bit.GPIO13 = 0;   // Enable pullup on GPIO13
	GpioDataRegs.GPASET.bit.GPIO13 = 1;   // Load output latch
	GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 0;  // GPIO13 = GPIO13
	GpioCtrlRegs.GPADIR.bit.GPIO13 = 1;   // GPIO13 = output

	//初始化 pwm和ecap
	InitEPwm5Gpio();
	InitECap3Gpio(9);
	GPIO_SetupPinOptions(9, GPIO_INPUT, GPIO_ASYNC);

	EALLOW;  // This is needed to write to EALLOW protected registers
	PieVectTable.ECAP3_INT = &ecap3_ISR;
	EDIS;    // This is needed to disable write to EALLOW protected registers

	InitEPwm5();
	InitECap3();


	//XINTRX = GPIO10
	// Make GPIO10 the input source for Xint1
	EALLOW;
	PieVectTable.XINT1_INT = &xintrx_ISR;
	EDIS;
	GPIO_SetupXINT1Gpio(10);    // Xint1 connected to GPIO10
	XintRegs.XINT1CR.bit.POLARITY = 1;
	XintRegs.XINT1CR.bit.ENABLE = 1;

	// Configure GPIO48 as a GPIO output pin
	EALLOW;
	GpioCtrlRegs.GPBMUX2.bit.GPIO48 = 0;
	GpioCtrlRegs.GPBDIR.bit.GPIO48 = 1;
	EDIS;

	IER |= M_INT1;
//	PieCtrlRegs.PIEIER1.bit.INTx4 = 1;
	IER |= M_INT4;
	PieCtrlRegs.PIEIER4.bit.INTx3 = 1;

	EINT;
	ERTM;

	CreateSysTimerInterface()->Start(inport,2u);
}