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CCS/TMS320F280049: Synchronising ADC's and PWM's for DC Converter application

Ponsonby Rivers
Intellectual 620 points
Part Number: TMS320F280049


Tool/software: Code Composer Studio

Can someone please offer software structure suggestions on how I can realise the following for a Bi-Directional Interleaved Buck-Boost DC/DC Converter operating at 100kHz.

EPWM1 and EPWM2 = Phase 1 (0deg)
EPWM3 and EPWM4 = Phase 2 (120deg)
EPWM5 and EPWM6 = Phase 3 (240deg)

ADC A:
- Inductor current phase 1
- Vin
- Vout

ADC B:
- Inductor current phase 2
- Vout
- Iout
- Temp1

ADC C:
- Inductor current phase 3
- Iin
- Vother
- Temp2

Bear in mind, the above ADC arrangement cannot change as the board has been fabricated.

Requirement:
- inductor currents are required to be sampled at 900ksps
- voltages and currents are required to be sampled at 100ksps x 3
- temperature measurements are required to be sampled at 1sps

All ADC's need to be synchronised with the EPWM's and operate in a synchronous fashion.
Inductor currents are supplied to the CMPSS as part of the peak current control algorithm.
The CLA will perform the 2p2z compensation for each phase every 10us (1/100kHz).
CAN bus to operate on the CPU.

What I've done thus far:
Build configuration is set to Flash as I obtain code size errors with RAM.
CAN bus functions correctly on CPU every 10ms which uses CPU Timer1
EPWM's function correctly and are out of phase 120deg for fixed duty cycles.
Control algorithm has not been implemented at the time of writing.
I have modified the cla_ex1_adc_fir example for the ADC arrangement.
The ADC is triggering on EPWM7.
There are 3 CLA tasks plus a fourth for initialising variables.
CLA Task 1 is used for Inductor current processing (trigger on ADCA1).
CLA Task 2 is used for voltages and currents processing (trigger on ADCB1). This is where the 2p2z will be unless recommended otherwise.
CLA Task 3 is used for temperature processing (trigger on ADCC1).

I'd like input in how I can correctly initialise the ADC.

  • 0
    TI__Expert 6965 points

    If you want your ADC sampling to be synchronized to a specific phase of your PWM, then use ePWM to generate the SOC signal in the desired time and let the SOC to trigger your corresponding ADC conversion. Then the control ISR / Task can be triggered by ADC-EOC singal.

    Hope this helps, and please give additional details about the timing sequence you would like to achieve if you want more detailed consultant. Thanks.

    Han

  • 0 in reply to Han Zhang6
    Intellectual 620 points

    Understanding that the ADC sampling can be synchronized to a specific phase of a PWM, the input/output voltage/current values (4 in total) are required for EPWM1/2, EPWM3/4 and EPWM5/6. From what I understand, the ADC can not have multiple sources of triggers. I have used EPWM7 sampled at 300kHz (3 x 100kHz) to capture points in this sequence and monitor TBPRD to process the correct phase at a particular point in time. Currently, I have EPWM1 set to the master to synchronize all PWM signals including EPWM7. Is this the correct method for synchronizing all PWM's?

    I have updated the CLA tasks to generate an interrupt at the end of an ADC conversion. The following is using EPWM7 as the trigger source.
    CLA Task 1 - Iin
    CLA Task 2 - Vin
    CLA Task 3 - Iout
    CLA Task 4 - Vout
    Each of the above tasks perform a 2p2z biquad filter however, post processing is required once all the four parameters have been converted. I would like to perform the post processing on one of these tasks only. Should I make (say) Task 4 the least priority ADC conversion and then perform the post processing in this task? Your thoughts.

    The below tasks are triggered on CPUTimer0 at 900ksps.
    CLA Task 5 - Inductor current phase 1
    CLA Task 6 - Inductor current phase 2
    CLA Task 7 - Inductor current phase 3
    After each completion of the tasks, I toggle a pin on the uC to check timing correctness. With all the above running, there is misalignment and my CPUTimer1 (used to process CAN functions) no longer operates. Furthermore, between Task1 and Task 2 there is a lag of approximately 1us and it appears the other signals are not synchronized. Is this expected? When I reduce the ADC trigger frequencies in the kHz region, there is no misalignment however, there is still a 1us lag between signals.

  • 0 in reply to Ponsonby Rivers
    Intellectual 620 points

    Does anyone have any feedback on my queries?