Part Number: TMS320F28377D
Other Parts Discussed in Thread: C2000WARE
Dear Champs,
I am asking this for our customer.
In TRM, it says
(Note that the link to F28377D TRM (http://www.ti.com/lit/pdf/SPRUHM8) seems to have something wrong now on ti.com. I use F28377S TRM (http://www.ti.com/lit/ug/spruhx5g/spruhx5g.pdf) instead here to discuss first.)
Enabling Interrupts
To enable a peripheral interrupt, perform the following steps:
1. Disable interrupts globally (DINT or SETC INTM).
2. Enable the PIE by setting the ENPIE bit of the PIECTRL register.
3. Write the ISR vector for each interrupt to the appropriate location in the PIE vector table, which can be found in Table 3-2.
4. Set the appropriate PIEIERx bit for each interrupt. The PIE group and channel assignments can be found in Table 3-2.
5. Set the CPU IER bit for any PIE group containing enabled interrupts.
6. Enable the interrupt in the peripheral.
7. Enable interrupts globally (EINT or CLRC INTM).
However, in our codes, say
C:\TI\c2000\C2000Ware_2_00_00_03\device_support\f2837xd\examples\cpu1\timed_led_blink\cpu01\LEDBlink.c
We use it like this.
//
// Enable CPU INT1 which is connected to CPU-Timer 0:
//
IER |= M_INT1;
//
// Enable TINT0 in the PIE: Group 1 __interrupt 7
//
PieCtrlRegs.PIEIER1.bit.INTx7 = 1;
Questions:
The order of step 3 and step 4 is different from that in our example codes.
What is the right order we suggest?
Or it doesn't matter, and both orders are OK?
Wayne Huang
