Tool/software: Code Composer Studio
I am having a problem in shadow mode of PWM module
* Requires PWM channel
+ PWM pulse has a frequency of 5kHz.
+ Duty is 20% and 60% for 2 consecutive cycles.
* I configure PWM module the following:
EALLOW;
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0;
EDIS;
pwm1.PeriodMax = (FREQUENCY_CLOCK_PWM/(2*SVM_SYSTEM)); /* Initializa ePWM */
//---------------------PWM1-----------------------------------------
EALLOW;
EPwm1Regs.TBPRD = pwm1.PeriodMax; // Set timer periodEPwm1Regs.TBPHS.bit.TBPHS = 0x0000; // Phase is 0
EPwm1Regs.TBCTR = 0x0000; // Clear counter
//
// Setup TBCLK
//
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load registers every ZERO
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADAMODE = ET_CTR_ZERO;
EPwm1Regs.CMPCTL.bit.LOADBMODE = ET_CTR_ZERO;
//
// Set actions
//
EPwm1Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM1A on Zero
EPwm1Regs.AQCTLA.bit.CAD = AQ_CLEAR;
//
// Active Low PWMs - Setup Deadband
//
EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
EPwm1Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm1Regs.DBRED.bit.DBRED = 100;
EPwm1Regs.DBFED.bit.DBFED = 100;
EPwm1Regs.ETSEL.bit.SOCAEN = 1;
EPwm1Regs.ETSEL.bit.SOCASEL = ET_CTR_ZERO; /* CTR = 0*/
EPwm1Regs.ETPS.bit.SOCAPRD = ET_1ST; /* Generate pulse on 1st event*/
EPwm1Regs.ETCLR.bit.SOCA = 1;
EPwm1Regs.ETPS.bit.SOCACNT = ET_1ST ; /* Generate INT on 2rd event */
EDIS;
EALLOW;
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1;
EDIS;
* Result:
The pulse width from the PWM channel is 40% (it seems to be the average of 20% and 60%).
Note: When I use immediate load mode for PWM, the result is correct. But in my project, the pulse from the PWM channel must be set to shadow mode.
