Part Number: TMS320F28377D
Tool/software: Code Composer Studio
I use 28377 EMIF to connect Dual port RAM for asynchronous communication. The busy pin of Dual port RAM is connected to theEM1WAIT Pin of 28377. Because the manual only describes the wait mode in words, and there is no sequence diagram. I hope you can draw a brief sequence diagram to let me understand the correct sequence logic of 28377's EMIF bus when the wait pin gets low.Because I have observed that when the busy signal jumps to a low level, the EMIF bus does not wait. So I expect to know when the busy level becomes low, and then the EMIF bus will wait.
//Configure the access timing for CS2 space
//
Emif1Regs.ASYNC_CS2_CR.all = (EMIF_ASYNC_ASIZE_16 | // 16Bit Memory
// Interface
EMIF_ASYNC_TA_2 | // Turn Around time
// of 2 Emif Clock
EMIF_ASYNC_RHOLD_2 | // Read Hold time
// of 2 Emif Clock
EMIF_ASYNC_RSTROBE_8 | // Read Strobe time
// of 8 Emif Clock
EMIF_ASYNC_RSETUP_2 | // Read Setup time
// of 2 Emif Clock
EMIF_ASYNC_WHOLD_2 | // Write Hold time
// of 2 Emif Clock
EMIF_ASYNC_WSTROBE_8 | // Write Strobe time
// of 8 Emif Clock
EMIF_ASYNC_WSETUP_2 | // Write Setup time
// of 2 Emif Clock
EMIF_ASYNC_EW_ENABLE | // Extended Wait
// Enable.
EMIF_ASYNC_SS_DISABLE // Strobe Select Mode
// Disable.
);
Emif1Regs.ASYNC_WCCR.bit.WP0=0;
//The max wait time for (max_ext_wait + 1) * 16 clock cycles before the busy signal goto high
Emif1Regs.ASYNC_WCCR.bit.MAX_EXT_WAIT=0x80;
//enable AT,LT interrupt,disable WR interrupt
Emif1Regs.INT_MSK_SET.bit.AT_MASK_SET=1;
Emif1Regs.INT_MSK_CLR.bit.WR_MASK_CLR=1;
Emif1Regs.INT_MSK_SET.bit.LT_MASK_SET=1;
