Other Parts Discussed in Thread: CONTROLSUITE
Hello,
I am working on DRV830x-HC-C2-KIT which is based on TMS320F28035. I have exceeded the maximum RAM size and need to run the code from FLASH.
Despite of my various tries, I still have not succeed to run code from flash. My actions are as follows in summary:
1) I've followed the controlSuite example (Example_2803xFlashProgramming) and copied the Example_Flash28035_ROM_API.cmd file to my project with corresponding libs.
2) I've defined the FLASH from CCS Properties - Predefined Symbols to be able to copy time critical code and Flash setup code to RAM.
3) Also, I've included the DSP2803x_CodeStartBranch.asm to my project for proper code starting.
4) And I changed the SECTION .text from .text: > FLASHA PAGE = 0 to .text : >> FLASHA | FLASHC | FLASHD PAGE = 0
In final situtation, I can program and debug my code with CCS but I am unable to run my program stand alone. (after turn off and turn on the power)
Also, I tried to determine where it is fails with "load symbols only" but unfortunately then I got following error: "No source available for "0x3ff8a1"
Here is my Example_Flash28035_ROM_API.cmd
/* //########################################################################### // // FILE: Example_2803xFlashProgramming.cmd // // TITLE: Linker Command File For F28035 Device Flash API // //########################################################################### // $TI Release: F2803x C/C++ Header Files and Peripheral Examples V130 $ // $Release Date: May 8, 2015 $ // $Copyright: Copyright (C) 2009-2015 Texas Instruments Incorporated - // http://www.ti.com/ ALL RIGHTS RESERVED $ //########################################################################### */ /* ====================================================== // For Code Composer Studio V2.2 and later // --------------------------------------- // In addition to this memory linker command file, // add the header linker command file directly to the project. // The header linker command file is required to link the // peripheral structures to the proper locations within // the memory map. // // The header linker files are found in <base>\DSP2803x_Headers\cmd // // For nonBIOS applications add: DSP2803x_Headers_nonBIOS.cmd ========================================================= */ /* Define the memory block start/length for the F2803x PAGE 0 will be used to organize program sections PAGE 1 will be used to organize data sections Notes: Memory blocks on F2803x are uniform (ie same physical memory) in both PAGE 0 and PAGE 1. That is the same memory region should not be defined for both PAGE 0 and PAGE 1. Doing so will result in corruption of program and/or data. L0/L1/L2 and L3 memory blocks are mirrored - that is they can be accessed in high memory or low memory. For simplicity only one instance is used in this linker file. Contiguous SARAM memory blocks can be combined if required to create a larger memory block. */ MEMORY { PAGE 0: /* Program Memory */ /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */ PRAML0 : origin = 0x008000, length = 0x000800 /* on-chip RAM block L0 */ OTP : origin = 0x3D7800, length = 0x000400 /* on-chip OTP */ FLASHD : origin = 0x3F4000, length = 0x001000 /* on-chip FLASH */ FLASHC : origin = 0x3F5000, length = 0x001000 /* on-chip FLASH */ FLASHA : origin = 0x3F7000, length = 0x000F80 /* on-chip FLASH */ CSM_RSVD : origin = 0x3F7F80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */ BEGIN : origin = 0x3F7FF6, length = 0x000002 /* Part of FLASHA. Used for "boot to Flash" bootloader mode. */ CSM_PWL_PROG: origin = 0x3F7FF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */ IQTABLES : origin = 0x3FE000, length = 0x000B50 /* IQ Math Tables in Boot ROM */ IQTABLES2 : origin = 0x3FEB50, length = 0x00008C /* IQ Math Tables in Boot ROM */ IQTABLES3 : origin = 0x3FEBDC, length = 0x0000AA /* IQ Math Tables in Boot ROM */ ROM : origin = 0x3FF27C, length = 0x000D44 /* Boot ROM */ RESET : origin = 0x3FFFC0, length = 0x000002 /* part of boot ROM */ VECTORS : origin = 0x3FFFC2, length = 0x00003E /* part of boot ROM */ PAGE 1 : /* Data Memory */ /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */ /* Registers remain on PAGE1 */ BOOT_RSVD : origin = 0x000000, length = 0x000050 /* Part of M0, BOOT rom will use this for stack */ RAMM0 : origin = 0x000050, length = 0x0003B0 /* on-chip RAM block M0 */ RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ DRAML0 : origin = 0x008800, length = 0x000800 /* on-chip RAM block L0 */ FLASHB : origin = 0x3F6000, length = 0x001000 /* on-chip FLASH */ } /* Allocate sections to memory blocks. Note: codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code execution when booting to flash ramfuncs user defined section to store functions that will be copied from Flash into RAM */ SECTIONS { /* Allocate program areas: */ /* The Flash API functions can be grouped together as shown below. The defined symbols _Flash28_API_LoadStart, _Flash28_API_LoadEnd and _Flash28_API_RunStart are used to copy the API functions out of flash memory and into SARAM */ .cinit : > FLASHA PAGE = 0 .pinit : > FLASHA, PAGE = 0 .text : >> FLASHA | FLASHC | FLASHD PAGE = 0 codestart : > BEGIN PAGE = 0 ramfuncs : LOAD = FLASHA, RUN = PRAML0, LOAD_START(_RamfuncsLoadStart), LOAD_END(_RamfuncsLoadEnd), RUN_START(_RamfuncsRunStart), PAGE = 0 csmpasswds : > CSM_PWL_PROG PAGE = 0 csm_rsvd : > CSM_RSVD PAGE = 0 /* Allocate uninitalized data sections: */ .stack : > RAMM0 PAGE = 1 .ebss : > DRAML0 PAGE = 1 .esysmem : > DRAML0 PAGE = 1 /* Initalized sections go in Flash */ /* For SDFlash to program these, they must be allocated to page 0 */ .econst : > FLASHA PAGE = 0 .switch : > FLASHA PAGE = 0 /* Allocate IQ math areas: */ IQmath : > FLASHA PAGE = 0 /* Math Code */ IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD /* Uncomment the section below if calling the IQNexp() or IQexp() functions from the IQMath.lib library in order to utilize the relevant IQ Math table in Boot ROM (This saves space and Boot ROM is 1 wait-state). If this section is not uncommented, IQmathTables2 will be loaded into other memory (SARAM, Flash, etc.) and will take up space, but 0 wait-state is possible. */ /* IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD { IQmath.lib<IQNexpTable.obj> (IQmathTablesRam) } */ /* Uncomment the section below if calling the IQNasin() or IQasin() functions from the IQMath.lib library in order to utilize the relevant IQ Math table in Boot ROM (This saves space and Boot ROM is 1 wait-state). If this section is not uncommented, IQmathTables2 will be loaded into other memory (SARAM, Flash, etc.) and will take up space, but 0 wait-state is possible. */ /* IQmathTables3 : > IQTABLES3, PAGE = 0, TYPE = NOLOAD { IQmath.lib<IQNasinTable.obj> (IQmathTablesRam) } */ /* .reset is a standard section used by the compiler. It contains the */ /* the address of the start of _c_int00 for C Code. /* /* When using the boot ROM this section and the CPU vector */ /* table is not needed. Thus the default type is set here to */ /* DSECT */ .reset : > RESET, PAGE = 0, TYPE = DSECT vectors : > VECTORS PAGE = 0, TYPE = DSECT } /* //=========================================================================== // End of file. //=========================================================================== */
Here is my DSP2803x_Headers_nonBIOS.cmd
/*
// TI File $Revision: /main/3 $
// Checkin $Date: November 10, 2009 14:05:22 $
//###########################################################################
//
// FILE: DSP2803x_Headers_nonBIOS.cmd
//
// TITLE: DSP2803x Peripheral registers linker command file
//
// DESCRIPTION:
//
// This file is for use in Non-BIOS applications.
//
// Linker command file to place the peripheral structures
// used within the DSP2803x headerfiles into the correct memory
// mapped locations.
//
// This version of the file includes the PieVectorTable structure.
// For BIOS applications, please use the DSP2803x_Headers_BIOS.cmd file
// which does not include the PieVectorTable structure.
//
//###########################################################################
// $TI Release: 2803x C/C++ Header Files and Peripheral Examples V1.24 $
// $Release Date: January 11, 2011 $
//###########################################################################
*/
MEMORY
{
PAGE 0: /* Program Memory */
PAGE 1: /* Data Memory */
DEV_EMU : origin = 0x000880, length = 0x000105 /* device emulation registers */
SYS_PWR_CTL : origin = 0x000985, length = 0x000003 /* System power control registers */
FLASH_REGS : origin = 0x000A80, length = 0x000060 /* FLASH registers */
CSM : origin = 0x000AE0, length = 0x000010 /* code security module registers */
ADC_RESULT : origin = 0x000B00, length = 0x000020 /* ADC Results register mirror */
CPU_TIMER0 : origin = 0x000C00, length = 0x000008 /* CPU Timer0 registers */
CPU_TIMER1 : origin = 0x000C08, length = 0x000008 /* CPU Timer0 registers (CPU Timer1 & Timer2 reserved TI use)*/
CPU_TIMER2 : origin = 0x000C10, length = 0x000008 /* CPU Timer0 registers (CPU Timer1 & Timer2 reserved TI use)*/
PIE_CTRL : origin = 0x000CE0, length = 0x000020 /* PIE control registers */
PIE_VECT : origin = 0x000D00, length = 0x000100 /* PIE Vector Table */
CLA1 : origin = 0x001400, length = 0x000080 /* CLA registers */
ECANA : origin = 0x006000, length = 0x000040 /* eCAN-A control and status registers */
ECANA_LAM : origin = 0x006040, length = 0x000040 /* eCAN-A local acceptance masks */
ECANA_MOTS : origin = 0x006080, length = 0x000040 /* eCAN-A message object time stamps */
ECANA_MOTO : origin = 0x0060C0, length = 0x000040 /* eCAN-A object time-out registers */
ECANA_MBOX : origin = 0x006100, length = 0x000100 /* eCAN-A mailboxes */
COMP1 : origin = 0x006400, length = 0x000020 /* Comparator + DAC 1 registers */
COMP2 : origin = 0x006420, length = 0x000020 /* Comparator + DAC 2 registers */
COMP3 : origin = 0x006440, length = 0x000020 /* Comparator + DAC 3 registers */
EPWM1 : origin = 0x006800, length = 0x000040 /* Enhanced PWM 1 registers */
EPWM2 : origin = 0x006840, length = 0x000040 /* Enhanced PWM 2 registers */
EPWM3 : origin = 0x006880, length = 0x000040 /* Enhanced PWM 3 registers */
EPWM4 : origin = 0x0068C0, length = 0x000040 /* Enhanced PWM 4 registers */
EPWM5 : origin = 0x006900, length = 0x000040 /* Enhanced PWM 5 registers */
EPWM6 : origin = 0x006940, length = 0x000040 /* Enhanced PWM 6 registers */
EPWM7 : origin = 0x006980, length = 0x000040 /* Enhanced PWM 7 registers */
ECAP1 : origin = 0x006A00, length = 0x000020 /* Enhanced Capture 1 registers */
EQEP1 : origin = 0x006B00, length = 0x000040 /* Enhanced QEP 1 registers */
LINA : origin = 0x006C00, length = 0x000080 /* LIN-A registers */
GPIOCTRL : origin = 0x006F80, length = 0x000040 /* GPIO control registers */
GPIODAT : origin = 0x006FC0, length = 0x000020 /* GPIO data registers */
GPIOINT : origin = 0x006FE0, length = 0x000020 /* GPIO interrupt/LPM registers */
SYSTEM : origin = 0x007010, length = 0x000020 /* System control registers */
SPIA : origin = 0x007040, length = 0x000010 /* SPI-A registers */
SPIB : origin = 0x007740, length = 0x000010 /* SPI-B registers */
SCIA : origin = 0x007050, length = 0x000010 /* SCI-A registers */
NMIINTRUPT : origin = 0x007060, length = 0x000010 /* NMI Watchdog Interrupt Registers */
XINTRUPT : origin = 0x007070, length = 0x000010 /* external interrupt registers */
ADC : origin = 0x007100, length = 0x000080 /* ADC registers */
I2CA : origin = 0x007900, length = 0x000040 /* I2C-A registers */
PARTID : origin = 0x3D7E80, length = 0x000001 /* Part ID register location */
CSM_PWL : origin = 0x3F7FF8, length = 0x000008 /* Part of FLASHA. CSM password locations. */
}
SECTIONS
{
/*** PIE Vect Table and Boot ROM Variables Structures ***/
UNION run = PIE_VECT, PAGE = 1
{
PieVectTableFile
GROUP
{
EmuKeyVar
EmuBModeVar
FlashCallbackVar
FlashScalingVar
}
}
/*** Peripheral Frame 0 Register Structures ***/
DevEmuRegsFile : > DEV_EMU, PAGE = 1
SysPwrCtrlRegsFile: > SYS_PWR_CTL, PAGE = 1
FlashRegsFile : > FLASH_REGS, PAGE = 1
CsmRegsFile : > CSM, PAGE = 1
AdcResultFile : > ADC_RESULT, PAGE = 1
CpuTimer0RegsFile : > CPU_TIMER0, PAGE = 1
CpuTimer1RegsFile : > CPU_TIMER1, PAGE = 1
CpuTimer2RegsFile : > CPU_TIMER2, PAGE = 1
PieCtrlRegsFile : > PIE_CTRL, PAGE = 1
Cla1RegsFile : > CLA1, PAGE = 1
/*** Peripheral Frame 1 Register Structures ***/
ECanaRegsFile : > ECANA, PAGE = 1
ECanaLAMRegsFile : > ECANA_LAM, PAGE = 1
ECanaMboxesFile : > ECANA_MBOX, PAGE = 1
ECanaMOTSRegsFile : > ECANA_MOTS, PAGE = 1
ECanaMOTORegsFile : > ECANA_MOTO, PAGE = 1
ECap1RegsFile : > ECAP1, PAGE = 1
EQep1RegsFile : > EQEP1, PAGE = 1
LinaRegsFile : > LINA, PAGE = 1
GpioCtrlRegsFile : > GPIOCTRL, PAGE = 1
GpioDataRegsFile : > GPIODAT, PAGE = 1
GpioIntRegsFile : > GPIOINT, PAGE = 1
/*** Peripheral Frame 2 Register Structures ***/
SysCtrlRegsFile : > SYSTEM, PAGE = 1
SpiaRegsFile : > SPIA, PAGE = 1
SpibRegsFile : > SPIB, PAGE = 1
SciaRegsFile : > SCIA, PAGE = 1
NmiIntruptRegsFile: > NMIINTRUPT, PAGE = 1
XIntruptRegsFile : > XINTRUPT, PAGE = 1
AdcRegsFile : > ADC, PAGE = 1
I2caRegsFile : > I2CA, PAGE = 1
/*** Peripheral Frame 3 Register Structures ***/
Comp1RegsFile : > COMP1, PAGE = 1
Comp2RegsFile : > COMP2, PAGE = 1
Comp3RegsFile : > COMP3, PAGE = 1
EPwm1RegsFile : > EPWM1, PAGE = 1
EPwm2RegsFile : > EPWM2, PAGE = 1
EPwm3RegsFile : > EPWM3, PAGE = 1
EPwm4RegsFile : > EPWM4, PAGE = 1
EPwm5RegsFile : > EPWM5, PAGE = 1
EPwm6RegsFile : > EPWM6, PAGE = 1
EPwm7RegsFile : > EPWM7, PAGE = 1
/*** Code Security Module Register Structures ***/
CsmPwlFile : > CSM_PWL, PAGE = 1
/*** Device Part ID Register Structures ***/
PartIdRegsFile : > PARTID, PAGE = 1
}
/*
//===========================================================================
// End of file.
//===========================================================================
*/
Here is my DSP2803x_CodeStartBranch.asm:
;//###########################################################################
;//
;// FILE: DSP2803x_CodeStartBranch.asm
;//
;// TITLE: Branch for redirecting code execution after boot.
;//
;// For these examples, code_start is the first code that is executed after
;// exiting the boot ROM code.
;//
;// The codestart section in the linker cmd file is used to physically place
;// this code at the correct memory location. This section should be placed
;// at the location the BOOT ROM will re-direct the code to. For example,
;// for boot to FLASH this code will be located at 0x3f7ff6.
;//
;// In addition, the example DSP2803x projects are setup such that the codegen
;// entry point is also set to the code_start label. This is done by linker
;// option -e in the project build options. When the debugger loads the code,
;// it will automatically set the PC to the "entry point" address indicated by
;// the -e linker option. In this case the debugger is simply assigning the PC,
;// it is not the same as a full reset of the device.
;//
;// The compiler may warn that the entry point for the project is other then
;// _c_init00. _c_init00 is the C environment setup and is run before
;// main() is entered. The code_start code will re-direct the execution
;// to _c_init00 and thus there is no worry and this warning can be ignored.
;//
;//###########################################################################
;// $TI Release: F2803x C/C++ Header Files and Peripheral Examples V130 $
;// $Release Date: May 8, 2015 $
;// $Copyright: Copyright (C) 2009-2015 Texas Instruments Incorporated -
;// http://www.ti.com/ ALL RIGHTS RESERVED $
;//###########################################################################
***********************************************************************
WD_DISABLE .set 1 ;set to 1 to disable WD, else set to 0
.ref _c_int00
.global code_start
***********************************************************************
* Function: codestart section
*
* Description: Branch to code starting point
***********************************************************************
.sect "codestart"
code_start:
.if WD_DISABLE == 1
LB wd_disable ;Branch to watchdog disable code
.else
LB _c_int00 ;Branch to start of boot.asm in RTS library
.endif
;end codestart section
***********************************************************************
* Function: wd_disable
*
* Description: Disables the watchdog timer
***********************************************************************
.if WD_DISABLE == 1
.text
wd_disable:
SETC OBJMODE ;Set OBJMODE for 28x object code
EALLOW ;Enable EALLOW protected register access
MOVZ DP, #7029h>>6 ;Set data page for WDCR register
MOV @7029h, #0068h ;Set WDDIS bit in WDCR to disable WD
EDIS ;Disable EALLOW protected register access
LB _c_int00 ;Branch to start of boot.asm in RTS library
.endif
;end wd_disable
.end
;//===========================================================================
;// End of file.
;//===========================================================================
Here is my CCS General Settings
So, I'm stuck here and thank you very much in advance for any suggestions to detect the problem.
