Hi,
What will be the content of the RAM location after a Reset of the DSP F28335.
I mean to say Reset, not the power cycle .
I could not find any related documents on the same.
Thanks,
Mohan
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Mohan,
This is correct from TI side as well; SRAM contents are random from power up(hard reset) and are maintained if normal reset is given(either from XRSn pin or debugger reset).
I had always assumed this is understood function of SRAM in general, but I am interested in your feedback if you have seen this not to be the case in other processors.
Best,
Matthew
Hi Matthew,
Thanks for your inputs,
In this link, they have special register to determine, the contents of the SRAM.
http://www.cypress.com/?id=4&rID=39458
Considering just RAM, the contents will be stored, until, the power is there.
But it depends on the design of the architecture. If the internal hardware is desinged
in such a way that, on receiving a reset signal, the power to the RAM to be removed.
Then, in that case, the contents of the RAM will be cleared on the reset.
Actually my requirement of this was to perform a Watchdog test, where I am supposed
to store the Watchdog test status and test enable data in RAM, as well need to
provide a solid evidence, stating that the data will not be lost, nor corrupt.
Matthew, Is there any TI document, which I can refer as an evidence for the same, even though,
its a intrinsic property of RAM.
Mohan,
I don't know of an explicit document from TI only because SRAM is assumed to behave in the manner I posted.
The Cypress part is the exception here, in the fact the RAM gets initialized to 0 on Reset, which is why they have it documented. This would have be implemented as special logic to do this outside the SRAM, which we do not have on our devices. If we ever did something like this we would have to document in the same manner.
Best,
Matthew