Part Number: TMS320F28335
Tool/software: Code Composer Studio
Hi,
I was trying to establish a half-duplex serial communication scheme from the said DSP to an FPGA board. I need some clarification on the GPIO functionality to clean up the synchronization part of the communication protocol.
Considering the example of GPIO36 configured as an output pin, say the pin is initially reset(Logic 0), and I wish to set it(logic0 to logic 1 transition), there are 2 ways to achieve this:
method 1: GpioDataRegs.GPBSET.bit.GPIO36 = 1; // writing to the GPBSET register.
method 2: GpioDataRegs.GPBDAT.bit.GPIO36 = 1; // writing to the GPBDAT register.
As the code is being executed sequentially, can you please comment on how many machine cycles it might take for the hardware pin to go high.
Also, I had been advised by a friend(could never cross-check this from a reference guide though), that the data register may not be written to as the instruction is executed and it may take affect at a much later point, when the RAM values are actually written to the real memory. This suggests that the delay(software instruction execution to hardware pin switching) may be large and most importantly "undeterministic" for method 2. Can you please comment if this makes sense. Also I will be very grateful if you could point to any appropriate reference guide for DSP-TMS320F28335.
EDIT1: Could it be that method 2 has a delay of several machine cycles compared to method 1 as we are accessing a single bit of the corresponding data register and must be using bit-banding. The bit banding register might take a while to update to the real Data register, which is connected to hardware? Just another dart in the dark. :-P
Thank you! :-)