Other Parts Discussed in Thread: TIDM-HV-1PH-DCAC
Tool/software: Code Composer Studio
Dear all,
I am having such a problem in writing a closed loop program for inverter control.
First of all, the inverter is a current source inverter, which requires that the inductor cannot be operated in an open circuit, so the overlap region is required in the PWM drive. I set the overlap time of 1 microsecond in the EV module, as shown in Figure 1, which should be the case under normal circumstances.
However, the program has such a problem, and it is found that the overlapping time of the two signals driven by the fundamental frequency is longer than 20 microseconds, which seriously affects the output.
Then I have found through many experiments that it is no problem to use the phase-locked loop program alone in the interrupt cycle instead of the closed loop, or when adding the phase-locked loop, the inner loop program in the double-loop program affects the overlapping time, for example, the following sentence.
/****** 内环P(inner loop P) ******/
PR_output[0] = _IQmpy(_IQ(Kp2),PR_input[0]);
When the Kp2 variable is of the float32 type, the pwm signal will be abnormal. When writing 0.06 directly or using #define Kp2 0.06, the pwm signal will not be a problem. What is the reason? The inner ring uses other regulators (PI, PR) to write the same problem, but the outer loop is no problem. Because I used to define the float32 type before I did IQ calculation.
I don't know exactly which part of the program is causing such a problem.Changes to the inner loop parameters can affect this overlap time, but it is also possible that problems elsewhere in the program have an impact on the overall. It is normal because I use the PLL alone for open loop control or when I don't use the PLL to provide phase angle for closed loop control.
The figures and ccs project of the pwm signal are shown in the attached below.
ZYY-Carrier modulation PLL double loop.rar
Kindly help.
Thank You in Advance.
