running on flash

Hello,

Have you tried using CCS to debug your application in flash?

ki

Gustavo,

Many reasons may contribute for a program written to flash to fail but, since you mentioned the flashing process occurred without any issues, it seems there may be issues with the program itself. The experts in the C2000 Forum will have better ideas about this, therefore I will move your post there.

In the meantime, could you please give more information that can help further debug this issue? What is the version of CCS and the device being used? What examples are you seeing this behaviour? Are you trying to flash to a development board or your custom hardware? What are exactly the problems you mentioned when tried to run the SPRA958I examples? Do the examples simply not work or do they build with errors? If you are getting build errors, could you send the complete output of the build process?

Regards,

Rafael

some usual steps needed to migrate a ram project to a flash project:

1. redefine linker command files. make sure all code and const are moved to flash sections. For example, 

MEMORY

{

PAGE 0:

    BEGINRAM: origin=0x0, length=0x2

    RAMM0: origin=0x2, length=0x3fe

    OTP: origin=0x380400, length=0x400

    FLASH: origin=0x300000, length=0x20000

    BEGINFLASH: origin=0x33fff6, length=0x2

    CSM_PWL: origin=0x3f7ff8, length=0x8

    IQTABLES: origin=0x3fe000, length=0xb50

    IQTABLES2: origin=0x3feb50, length=0x8c

    FPUTABLES: origin=0x3febdc, length=0x6a0

    ROM: origin=0x3ff27c, length=0xd44

    RESET: origin=0x3fffc0, length=0x2

    VECTORS: origin=0x3fffc2, length=0x3e

    RAML4L7: origin=0xc000, length=0x4000

    ADC_CAL: origin=0x380080, length=0x9

PAGE 1:

    FLASH_DATA: origin=0x320000, length=0x1fff6

    RAML0L3: origin=0x8000, length=0x4000

    RAMM1: origin=0x400, length=0x400

}

SECTIONS

{

    .vectors: load = 0x000000000

    .switch: > FLASH, PAGE = 0

    .text: > FLASH, PAGE = 0

    .bss: > RAML0L3, PAGE = 1

    .ebss: > RAML0L3, PAGE = 1

    .far: > RAML0L3, PAGE = 1

    .cinit: > FLASH, PAGE = 0

    .pinit: > FLASH, PAGE = 0

    .const: > FLASH, PAGE = 0

    .econst: > FLASH, PAGE = 0

    .reset: > RESET, PAGE = 0, TYPE = DSECT

    .data: > RAML0L3, PAGE = 1

    .cio: > RAML0L3, PAGE = 1

    .sysmem: > RAML0L3, PAGE = 1

    .esysmem: > RAML0L3, PAGE = 1

    .stack: > RAMM1, PAGE = 1

    .rtdx_text: > FLASH, PAGE = 0

    .rtdx_data: > RAML0L3, PAGE = 1

    codestart: > BEGINFLASH, PAGE = 0

    csmpasswds: > CSM_PWL, PAGE = 0

    csm_rsvd: > RAMM0, PAGE = 0

    ramfuncs: LOAD = FLASH,

RUN = RAML4L7,

LOAD_START(_RamfuncsLoadStart),

LOAD_END(_RamfuncsLoadEnd),

RUN_START(_RamfuncsRunStart),

PAGE = 0

    ramdata: LOAD = FLASH_DATA,

RUN = RAML0L3,

LOAD_START(_RamdataLoadStart),

LOAD_END(_RamdataLoadEnd),

RUN_START(_RamdataRunStart),

PAGE = 1

    IQmath: LOAD = FLASH,

RUN = RAML4L7,

LOAD_START(_IQmathLoadStart),

LOAD_END(_IQmathLoadEnd),

RUN_START(_IQmathRunStart),

PAGE = 0

    .adc_cal: > ADC_CAL, PAGE = 0 , TYPE = NOLOAD

    IQmathTables: > IQTABLES, PAGE = 0 , TYPE = NOLOAD

    IQmathTables2: > IQTABLES2, PAGE = 0 , TYPE = NOLOAD

    FPUmathTables: > FPUTABLES, PAGE = 0 , TYPE = NOLOAD

    DMA_SEC_B: load = 0xFFF0, PAGE = 0

    DMA_SEC_A: load = 0xFFEE, PAGE = 0

}

-l "C:\Program Files (x86)\MATLAB\R2010b\toolbox\idelink\extensions\ticcs\c2000\c2833xPeripherals.cmd"

2. copy the InitFlash() to the RAM upon entering main

InitFlash() is defined in xxx_sysctrl.c. you would need to add #pragma CODE_SECTION(InitFlash, "ramfunction") at the top of the file to inform the linker the placement information.

you would define "ramfunction" section in the Linker command file so that it loads in flash but runs out of ram.

copy InitFlash() to the ram upon entering main. see spraau8 for detail.

3. call the  InitFlash()  function before your program starts.

hth

Hi Rafael!

I've been away because hollydays.

Answering your questions:

1 - CCS Version: 3.3.82.13

2 - Examples: F2812_example_nonBIOS_flash and F2812_example_nonBIOS_ram, availables in spra958i.zip file. The code for RAM runs perfectly, but not the code for FLASH.

3 - Is my custom hardware.

4 - The code for flash doesn't run. I can see clock in crystal, but nothing happens.

5 - The example for FLASH simply doesn't work, build is 100%.

Thanks and regards,

Gustavo.

hi

first u check command linker file, as said Leong, nothing is special except linker file,

check for any wait state required for access flash, it may happens flash is not initialized properly.

regards

nikhil

Hi Leong.

Are you using jtag interface and F28xx flash programm tool in CCS3?

Thanks,

Gustavo.

Yes I am. I did both the onboard xds v100 and a 510LC. with both ccs3.3 and v4. did you check your flash setup code and make sure everything required to run in RAM are copied over from flash at the start of the program?

Tks Leong. Mine is 510LC too.

I'm checking it again now. It shoul be, cause I'm using all F2812_example_nonBIOS_flash.pjt available in spra958i.zip. I have only changed LED pin, to blink one on my design. It worked for RAM project, so I suppose it should for flash too.

Leong,

I'm having sucess to write to flash and load symbols.

So I'm debuggind line-to-line, through F11. I reach

 LB _c_int00

and after that code remains in loop between two areas: one starting at 0x0066 goint to 0x0070 and jumps to 0x0011 (ITRAP0).

Does is say something to you?

Gustavo.

_c_int00 is in the ROM already... can you check your hardware boot selection pins gpio 84-87 are all LOWs (to select boot from flash) ?

Let's also make sure you are starting your program from the Flash. in the file xxx_CodeStartBranch.asm, there is a section of code defining the start point:

    .sect "codestart"

can you check your linker command file to make sure the "codestart" is mapped to the beginning of the flash location? In my file for 28335, i have BEGINFLASH: origin=0x33fff6, length=0x2

also check if you have linked the rts2800_fpu32.lib.

Gustavo,

i faced same problem with 28044, in that case pc first reach to codestart then jump to c_init_00 and suddenly goes to random

location having ITRAP0 instruction.

i found that because of  wait state for flash was less than required.

regards

nikhil

Thanks for the concise instructions, Leong. I had a similar problem, worked through your list and fixed it.

 Hi

I too have the same problem. Its haunting me for days now. I have followed all instructions given in spra958i in configuring my dsp to run from flash memory.

I use CCS V 3.3 On chip flash programmer. The programs is flashed correctly. But, none of the desired results are seen on the board. The same code works well with RAM .

I did some single stepping and found that , at the point the of program entry, (_c_int00) , an ITRAP is received and loops forever thereafter.

The processor I am using is a G silicon version of the tmsf2812.

I also have an E version of the same processor which is flashed using Flash API version 1.0. That works fine.

I have set all jumpers according to requirement.

MP/MC pin is pulled low.

SCITXDA pin is driven high.

I am posting my .cmd , codestart,copy sections  till _c_int00.

please help me get rid of this problem

2812.cmd

-c        /*case insensitive */
-m test.map
-stack 0x400  /* allot 400h  words for stack */               
                             

MEMORY
{
/* use this for internal program memory - H0SARAM    */

  /*PAGE 0 : PROG(R)     : origin = 0x3f8000, length = 0x1000 */
  /*PAGE 0 : PROG(R)     : origin = 0x3f8000, length = 0x1000 */
 PAGE 0:     BEGIN_FLASH : origin = 0x3F7FF6, length = 0x000002
 PAGE 0:    PROG_FLASH(R): origin = 0x3D8000, length = 0x1F00
 PAGE 0:    MORAM(RW)        :  origin = 0x000000, length = 0x400
 PAGE 0:    LORAM        :    origin=0x008000,length=0x800
/* use this for external RAM */
/*  PAGE 0 : PROG(R)     : origin = 0x100000, length = 0x80000 /*present in board*/
 
/*   PAGE 0 : PROG(R)     : origin = 0x3D8000, length = 0x2000 Flash*/

   PAGE 1 : M0RAM(RW)   : origin = 0x000000, length = 0x400
   PAGE 1 : M1RAM(RW)   : origin = 0x000400, length = 0x400
   PAGE 1 : L0L1RAM(RW) : origin = 0x008000, length = 0x2000
  
   /* PAGE 1 : VAR_RAM(RW) : origin = 0x000700, length = 0x3F*/
}
 
 SECTIONS
{
    /* 22-bit program sections */
     /*vectors     : {}     > VECTORS page=0 */
    .text        :         > PROG_FLASH  PAGE = 0
   
    /*16-Bit data sections
    .const   : > M0RAM, PAGE = 1*/
  
  
    .sysmem      :         > M0RAM, PAGE = 1
    .bss         :         > L0L1RAM, PAGE = 1
/*    .bss         :         > VAR_RAM, PAGE 1*/
    .stack      :         > M1RAM, PAGE = 1
    /*.table        :        > PROG_FLASH  PAGE = 0*/
    codestart    :         > BEGIN_FLASH, PAGE = 0
    copysections:         > PROG_FLASH, PAGE=0
    wddisable    :         > PROG_FLASH, PAGE=0
    secureRamFuncs: LOAD = PROG_FLASH    , PAGE = 0,
                    RUN =  LORAM        , PAGE = 0,
                    LOAD_START(_secureRamFuncs_loadstart),
                    LOAD_SIZE(_secureRamFuncs_loadsize),
                    RUN_START(_secureRamFuncs_runstart)

}
 


Code Start:

;// TI File $Revision:: 2    $
;//###########################################################################
;//
;// FILE:  DSP281x_CodeStartBranch.asm   
;//
;// TITLE: Branch for redirecting code execution after boot.
;//
;//###########################################################################
;// $TI Release: Flash281x API V2.10 $
;// $Release Date: August 4, 2005 $
;//###########################################################################    


***********************************************************************

WD_DISABLE    .set    1        ;set to 1 to disable WD, else set to 0

    .ref copy_sections
    .def code_start

***********************************************************************
* Function: codestart section
*
* Description: Branch to code starting point
***********************************************************************

    .sect "codestart"

code_start:
    .if WD_DISABLE == 1
        LB wd_disable       ;Branch to watchdog disable code
    .else
        LB copy_sections        ;Branch to start of boot.asm in RTS library
    .endif

;end codestart section


***********************************************************************
* Function: wd_disable
*
* Description: Disables the watchdog timer
***********************************************************************
    .if WD_DISABLE == 1

    .text
wd_disable:
    SETC OBJMODE        ;Set OBJMODE for 28x object code
    EALLOW              ;Enable EALLOW protected register access
    MOVZ DP, #7029h>>6  ;Set data page for WDCR register
    MOV @7029h, #0068h  ;Set WDDIS bit in WDCR to disable WD
    EDIS                ;Disable EALLOW protected register access
    LB copy_sections         ;Branch to start of boot.asm in RTS library

    .endif

;end wd_disable



    .end
   
; end of file CodeStartBranch.asm

Copy Flash Init to RAM :

;---------------------------------------------------------
; define a section to be copied from FLASH to RAM
;---------------------------------------------------------
    .def copy_sections
    .global _secureRamFuncs_loadstart,_secureRamFuncs_runstart,_secureRamFuncs_loadsize
    .ref   _c_int00,_flash_init
;---------------------------------------------------------
; copy .fir section from SLOW_MEM to FAST_MEM
;---------------------------------------------------------
    .sect "copysections"
copy_sections:

   
    MOVL XAR5,#_secureRamFuncs_loadsize                ; Store Section Size in XAR5
    SUBB XAR5,#1                        ; Subtract 1 in prep. for RPT instruction
    MOVL ACC,@XAR5                        ; Move Section Size to ACC
    MOVL XAR6,#_secureRamFuncs_loadstart            ; Store Load Starting Address in XAR6
    MOVL XAR7,#_secureRamFuncs_runstart            ; Store Run Address in XAR7
    LCR  copy

    LCR _flash_init

    LB _c_int00        ; Branch to start of boot.asm in RTS library

copy:
     B return,EQ       ; Return if ACC is Zero (No section to copy)

    RPT AL        ; Copy Section From Load Address to
    || PWRITE  *XAR7, *XAR6++   ; Run Address

return:
     LRETR        ; Return

 .end
;---------------------------------------------------------
; jump to section, now in RAM
;---------------------------------------------------------

FLASH INIT

       
   
    .include "reg_2812.h"
    .def _flash_init
    .sect "secureRamFuncs"

_flash_init:                        ;Initialise PWM

    POINT_FLASH

    MOV @FPWR,#03h                ;FLASH SET TO ACTIVE MODE (HIGH POWER)
    MOV @FSTATUS,#0100h            ;CLEAR THE 3VSTAT BIT
    MOV @FBANKWAIT,#0505h         ;RANDOM ACCESS WAIT STATES AND PAGED ACCESS WAIT STATES
    MOV @FOTPWAIT,#08h                   
   
   
;    /*** Force a complete pipeline flush to ensure that the write to the last register
;    configured occurs before returning. Safest thing is to wait 8 full cycles. ***/

    RPT #7 ; Do nothing for 8 cycles
    ||NOP
   

    LRETR

main.asm

 
             .include "var.inc"
            .include "reg_2812.h"
       
            .global _c_int00; global entry point for our code
            .ref initialize,_pwm_init
            .ref _adc_input,_dac_output  ;_flash_init
            .def _c_int02,_c_int03, UNUSED            ;Definition of Interrupt Vector

;T1 underflow is used as sampling frequency for adc

peakcurrent    .set      0600h                            ;peakcurrent value set for grid port.
                                                    ;upon reaching that value, all cmpr outputs are put in high Z state.


****************** MAIN starts******************************           
            .text
           
_c_int00:
       
    ;CLRC     DBGM
    ;C28ADDR                            ;C28 Addressing mode
    ;.c28_amode                        ;tell assembler this is c28 addressing mode
    ;C28OBJ                            ;C28 Object Mode
    ;EALLOW                            ;This is required for write access to memory mapped registers
    ;C28MAP                             ;ENABLE 28X MAPPING OF M0 M1 BLOCKS
   
   
   ; LCR    _copy_flash                ;vectors_flash_to_ram.asm       
    ;LCR    _flash_init                ;flash_config.asm
    LCR     initialize                ;do init.asm
    LCR     _pwm_init                ;pwm_init.asm
       
   

; Enable Interrupts
;Interrupt from peripheral passes through three levels.

    ;1)Peripheral Level
    POINT_EVA
                                    ;Enable T2 Compare Int   ;280h for uf and per match
    MOV     @EVAIMRB, #0002h        ;t2_cmpint are set to allow the peripheral interrupt request to the pie controller;page 146 spru065c
   
    POINT_EVB
    MOV        @EVBIMRA,#0200h            ;T3 UF Interrupt enabled  Pgae 144 spru065c
   
   
    ;2)PIE Level
    POINT_PERINT
   
    MOV        ACC,#0002h                ;T2CMPINT Enable                        INT3.2 ;page 130 spru078b
    MOV        @PIEIER3, ACC            ;Enable register enabled to pass request to CPU from corresponding peripheral.

    MOV        ACC,#0020h
    MOV        @PIEIER4, ACC            ;T3 Underflow Interrupt enabled            INT4.6 ;page 130 spru078b

    MOV        ACC, #0001h                ;Vectors fetched from pie vector table
    MOV        @PIECTRL, ACC

    POINT_EVA
    MOV        ACC, #0FFFFh            ;Reset EVAIFRB flag register
    MOV        @EVAIFRB, ACC
   
    POINT_EVB
    MOV        ACC, #0FFFFh            ;Reset EVBIFRA flag register
    MOV        @EVBIFRA, ACC


    ;3)CPU LEVEL
    MOVL    XAR0, #0Ch                ;INT 3 and int4  levels are enabled at cpu level ;page 135 spru078b
    PUSH    AR0                       
    POP        DBGIER                    ;DBGIER set for realtime,halted modes
    OR        IER, #0Ch                ;Set IER for Standard Mode;#4h
    CLRC    INTM                     ;INTM must be cleared to enable CPU Level Interrupts.

; END Enable Interrupts

inf_loop

    NOP
    B    inf_loop, UNC

*********************************************************
* END _c_int00 - Main Program (END RESET ISR)            *   
*********************************************************




*************************************************************
* ISR for Peak Current Control using T2CMPINT            *
*************************************************************

_c_int02:


    CLRC    DBGM            ;required only if debug is desired in ISR
    EALLOW
                               ;required to access protected memory mapped registers

***    For finding the execution time required for the code ***
   
    POINT_GPIO
    MOV        @GPBSET,#0800h     ;bit 11 of gpio port B.pin 4 of PDAC1,#02000h

*** For finding the execution time required for the code ***
   
    LCR     _adc_input
    LCR     _dac_output

    MOVW    DP, #xrefpeak
    MOV        AH,@xsensepeak
    CMP        AH,@xrefpeak                   
    B        shutdown, GT
   
    B        dontshut,UNC

shutdown
    POINT_EVB
    MOV    @ACTRB, #0000001000100000b
   
dontshut
   
   


;RESET PIE ACKNOWLEDGE BIT
    POINT_PERINT
    OR             @PIEACK, #04h            ;Level 3 CPU Interrupt       
    POINT_EVA
    ;OR         @EVAIFRA, #200h         ;writing 1 to the flag bit clears the bit; 280h for uf and permatch
    OR        @EVAIFRB,#0002h                ;required for further interrupts;3.2 in peripheral                               
       
    CLRC     INTM                        ;INTM to be cleared for enabling interrupts 

***    For finding the execution time required for the code ***
   
    POINT_GPIO
    MOV        @GPBCLEAR, #0800h    ;    bit 11 of gpio port B.pin 4 of PDAC1,#02000h

*** For finding the execution time required for the code ***   

    IRET                            ;exit from PWM ISR _c_int02:

*************************************************************
* END _c_int02 ISR                                            *

* T2CMPINT interrupt                                        *
*************************************************************

*********************************************************************
* ISR for Enabling the PWM pulses at the beginning of each PWM cycle*
*********************************************************************

_c_int03:


    CLRC    DBGM            ;required only if debug is desired in ISR
    EALLOW
                               ;required to access protected memory mapped registers

***    For finding the execution time required for the code ***
   
    POINT_GPIO
    MOV        @GPBSET,#0800h     ;bit 11 of gpio port B.pin 4 of PDAC1,#02000h

*** For finding the execution time required for the code ***

    POINT_EVB
    ;MOV        @COMCONB,#0A8F0h
    MOV    @ACTRB, #0000001000100010b
   
;RESET PIE ACKNOWLEDGE BIT
    POINT_PERINT
    OR         @PIEACK, #08h            ;required to receive interrupts from this level(level 4)
       
    POINT_EVB
    OR        @EVBIFRA,#0020h            ;required for further interrupts        4.6 level in peripheral                       
       
    CLRC     INTM                    ;INTM to be cleared for enabling interrupts 

***    For finding the execution time required for the code ***
   
    POINT_GPIO
    MOV        @GPBCLEAR, #0800h    ;    bit 11 of gpio port B.pin 4 of PDAC1,#02000h

*** For finding the execution time required for the code ***   

    IRET                            ;exit from PWM ISR _c_int03:

*************************************************************
* END _c_int03 ISR                                            *
* synchronization of the control algorithm with the PWM        *
* underflow interrupt                                        *
*************************************************************





















                                                                 
   
*************************************************************
* ISR for Other Interrupt                                     *
*************************************************************

UNUSED
    CLRC    DBGM
    NOP
    B        UNUSED, UNC             ;INFINITE LOOP. WATCHDOG WOULD RESET LATER

*********************************************************
* END UNUSED - ISR for Other Interrupt                    *   
*********************************************************
                                                          

Hi Deepak.

I solved the problem in the .cmd file. There was a section definition error, because original code was to run from RAM.

I´m away from my PC right. I´ll check your code later and compare to my.

Gustavo.

hi

I am usnig f28335, with ccs3.3 my code is bios based. its a motor control application that works fine in ram, and in flash too. Problems comes when i do Power reset to my board when i have downloaded code in flash. After power on reset i dont see pwm signal on scope used to run motor, while i can see them coming well from flash based code as long as power On Reset is not done. i have seen with hardware break point that after resetting the code in flash my code comes in isr only once, and then it does not come back in isr to generate PWM signals.Please help me in this regard

Shakeel