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TMS320F28379D: Changing the CPU cock speed

Ali Maknouninejad1
Prodigy 50 points

Part Number: TMS320F28379D

Hello,

I am working with a TMS320F28F379D, dual core DSP.

The original settings set the DSP work at 200MHz. For an application I need to reduce the cpu clock down to 60 MHZ, to reduce power consumption.

I tried to change the PLL settings at the file "F2837xD_SysCtrl.c":

#ifdef _LAUNCHXL_F28379D
InitSysPll(XTAL_OSC,IMULT_40,FMULT_0,PLLCLK_BY_2);
#else
InitSysPll(XTAL_OSC, IMULT_20, FMULT_0, PLLCLK_BY_2);
#endif // _LAUNCHXL_F28379D

I tried to change the IMULT_20, and PLLCLK_BY_2 to get the clock down to 60MHz. For instance, I tried IMULT_6, or IMULT_12, and PLLCLK_BY_4. I realized it realy doesn't matter what combination I try, if I set the clock less than 100MHZ, it just won't work. 

Could you please let me know how I can do this? And, are there other settings I need to apply if running the code either from RAM, or Flash?

Thanks,

Ali

  • 0
    TI__Guru 61235 points

    Ali,

    Per the device datasheet, sprs880k, Table 5-12, p.65, the PLL output should be between 120 and 400 MHz.

    Try this:

        InitSysPll(XTAL_OSC,IMULT_12,FMULT_0,PLLCLK_BY_2);

    The crystal on the launchpad is 10 MHz.  The above gives 120 MHz PLL output, 60 MHz SYSCLK.

    I just tried this on the F28377S launchpad with the Blinky example.  It works.  Should be same for F28379D launchpad.

    Regards,

    David

  • 0 in reply to David M. Alter
    Prodigy 50 points

    Hi David,

    Thanks for your reply.

    As I'm working with the experimental board, which has 20MHZ oscillator, I had to use IMULT_6, instead of IMULT_12 that you recommended for Launcpad. Though, it didn't work.

    Then, I changed it as follows, and it worked:

        InitSysPll(XTAL_OSC,IMULT_12,FMULT_0,PLLCLK_BY_4);

    That said, I pushed the PLL frequency before divider above 200MHz.

    Are there any particular cautions/ modifications I need to consider when changing the SysClk? Lets say, for running the code either from RAM, or Flash?

    Do I need to change the periherals (PWM, ADC, ...) clock dividers?

    Thanks,

    Ali

  • 0 in reply to Ali Maknouninejad1
    TI__Guru 61235 points

    Hi Ali,

    Didn't you say in your first post that IMULT_12 and PLLCLK_BY_4 didn't work?  It is working now?  These settings seem correct for 20 MHz OSCIN.

    >> Lets say, for running the code either from RAM, or Flash?

    >> Do I need to change the periherals (PWM, ADC, ...) clock dividers?

    You should set the flash wait-states as appropriate for the clock speed you are running at (e.g., 60 MHz).  Wait-state specs are given in the device datasheet.  For peripheral clocks, you may want to adjust LSPCLK, EPWMCLK, and HRPWMCLK to be equal to SYSCLK since SYSCLK is only 60 MHz.  If running at 200 MHz for example, you would have to set EPWMCLK=SYSCLK/2, since max EPWMCLK is 100 MHz.  But when running at only 60 MHz, you can have EPWMCLK equal to SYSCLK/1.  Table 5-12 in the datasheet contains the relevant clock specs.

    Regards,

    David

  • 0 in reply to David M. Alter
    Prodigy 50 points

    David,

    Sorry, my bad. I may have missed something. This time, when I set IMULT_12 and PLLCLK_BY_4 it is working.

    Thanks,

    Ali