• State TI Thinks Resolved
  • Locked Locked
  • Replies 3 replies
  • Answers 1 answer
  • Subscribers 81 subscribers
  • Views 271 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

CCS/F28M35H52C: Synchronization of multi F28M35H52C DSPs

Yong Zhou1
Intellectual 310 points
Part Number: F28M35H52C


Tool/software: Code Composer Studio

Hello, 

   I use TI F28M35H52 DSP to control a Buck (DC/DC) converter with N phases (N switches and N inductors).  To reduce the output current ripples, it adopts the interleaving technique to phase shift 360/N degree for each PWM signal.  My question is if I parallel M Buck converters to the same load but want to minimize the current ripples.  One possible solution is to interleaving each phase with 360 / (N* M) degree. Question is how could I synchronize multi F28M35H52C DSPs?  For example, the first F28M35H52C as master to output pulse to next F28M35H52C or all of F28M35H52C to synchronize them together, or any other means? 

  Thanks,

  Yong

  • 0
    TI__Guru 62975 points

    Yong,

    There is no native logic for synchronizing clocks between multiple DSPs. It may be possible to implement rough synchronization (within a few SYSCLK cycles of precision), but not an exact relationship.  The internal PLL and clock generation tree make it difficult to achieve perfect synchronization.

    The approach would be to use a clock fanout buffer to provide a single clock source to the DSPs.  The EPWM can respond to an external GPTRIP6 SYNCI signal for alignment.

    How many phases are you planning to implement?  Each DSP should have enough MIPS to support multiple phases with tighter control.

    -Tommy

  • 0 in reply to tlee
    Intellectual 310 points

    Hello, Tommy,

       Thank you for your answers.  I am interested in to knowing more about your suggestion to use a clock fanout buffer to provide a single clock source to the DSPs.  Could you please give me more specific procedure or technical notes about it?

       Yes, we have 4-6 phases and make sure each phase having enough MIPS.

       Thanks,

       Yong

  • 0 in reply to Yong Zhou1
    TI__Guru 62975 points

    Yong,

    I am not aware of any guides or official recommendations for doing this with C2000 devices.  It is more of a thought experiment.  A single clock source is helpful to reduce jitter that may occur if the device have different clock sources that drift in different directions.

    For two devices, you could probably use a single digital oscillator that is placed halfway between the two devices.  For more devices, a clock fanout buffer will be easier for managing signal integrity.

    If you are not required to use F28M35x, you may want to consider F2837x or F2838x.  The additional MIPS and improved analog integration would probably allow you to handle all 6 phases using a single device.

    -Tommy