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TMS320F28377D: ECC Logic Test for RAM using DxTEST register

Part Number: TMS320F28377D

Hi,

I am trying to test the RAM ECC logic using the test registers provided. Below is the sample algorithm that I am using but it is not working. The yellow highlighted statement does not write the anything to the memory. When DxTEST register is written with 0x10 or 0x55, the memory in the D0 RAM is not writable. I tried writing it using Expressions and Memory Browser windows.

Is this approach correct?

/* Pointer points to D0 RAM */

UINT16 *TestPointer = (UINT16*)0xB000;

/* Write to D0 RAM */
*TestPointer = 0x54;

EALLOW;

/* Enable test mode, write allowed only to data bits, not to ECC bits */
MemCfgRegs.DxTEST.all = 0x55;

/* Write bit flip data to the same memory */
*TestPointer = (0x54 ^ 1);

/* Read the Data */
ReadData = *TestPointer;

/* Disable test mode */
MemCfgRegs.DxTEST.bit.TEST_D0 = 0;

EDIS;

  • Hi Gobind,

    It should not happen that way. You should be able to update the memory location vis CCS memory watch window irrespective of the TEST_Dx value. Please note that if you are only updating one bit then read path will automatically correct it and show the corrected data hence you are seeing the same value. If you update more that one bit, you'll see that it's getting updated.

    Hope that clarifies it.

    Regards,

    Vivek Singh

  • Vivek,

    I tried writing more than one bits and it worked. So it corrects the single bit error the moment I write it. But now I am getting a processor reset after this if I run it continuously. If I go step by step, I dont see the reset (probably because it is disabled in debug mode). Can it be because the threshold value is 1?

    And is there any flag that I can check to see if the RAM ECC error has occurred?

    Should I get processor reset for single bit error also? or only double bit error?

    Please note: this is all with respect to RAM ECC test, NOT the Flash ECC test. Flash ECC test is working as expected.

    Thank you.

  • Now, I have seen the CERRFLG getting set for single bit error. But the problem is, it is giving me processor resets. Even if I clear the the flag immediately after the error occurs, it gives a processor reset. 

    Am I supposed to get resets for single bit errors as well? If yes, can I handle it without writing the interrupt handler?

  • Gobind,

    For uncorrectable error, NMI gets generated and if respective NMIFLG is not cleared then it'll issue a reset. We have ECC and Parity RAMs. For ECC, double (or more) bit error is un-correctable but for Parity RAMs, single bit error is un-correctable and will cause NMI and reset. You may be generating single bit error in parity RAM.

    Please refer the device document to get more detail on this.

    Regards,

    Vivek Singh

  • Hi Vivek,

    I am creating single bit error in the D0 RAM at the address 0x00B000. This is a dedicated RAM memory and it is ECC protected as per the section 3.11.1.1 of TRM. 

    Also, as I mentioned, I am able to see CERRFLG register getting set. This flag is for correctable errors only. Even CCPUREADDR register shows the address 0x00B000. I saw in the NMI registers, they were not getting set. So, I am pretty sure that it is a correctable error and in ECC protected RAM (NOT parity protected).

    Thank you.

  • If NMIFLG is not set then it can not be reset due to NMI. What is the status of watchdog ? Is it enable or disable. If enable then that can also cause reset if watchdog is not service at regular interval.

    Regards,

    Vivek Singh

  • Watchdog is disabled.

  • Ok, how do you know processor is getting reset?

    Vivek Singh

  • Gobind,

    Were you able to resolve this issue?

    Regards,

    Vivek Singh

  • Assuming you got this issue resolved hence marking the post closed.