Part Number: TMS320F28069M
Tool/software: TI C/C++ Compiler
I am calculating checksum for different sections in the linker file.
GROUP : > APP_FLASH, PAGE = 0, crc_table(_CRCTestVector,algorithm=CRC32_PRIME)
{
.cinit
.pinit
.binit
codestart
.text
/* Initalized sections to go in Flash */
/* For SDFlash to program these, they must be allocated to page 0 */
.econst
.switch
}
I am also calculating the checksum of application flash, once I program the flash using bootloader. The checksum matches for all the sections except for text sections.
I have compared the contents of .text section from memory dump, I see no change in the data. Can anyone help me regarding this. I am attaching linker cmd of my application file here
/*
//###########################################################################
//
// FILE: F28069.cmd
//
// TITLE: Linker Command File For F28069 Device
//
//###########################################################################
// $TI Release: F2806x C/C++ Header Files and Peripheral Examples V135 $
// $Release Date: Sep 8, 2012 $
//###########################################################################
*/
/* ======================================================
// For Code Composer Studio V2.2 and later
// ---------------------------------------
// In addition to this memory linker command file,
// add the header linker command file directly to the project.
// The header linker command file is required to link the
// peripheral structures to the proper locations within
// the memory map.
//
// The header linker files are found in <base>\F2806x_headers\cmd
//
// For BIOS applications add: F2806x_Headers_BIOS.cmd
// For nonBIOS applications add: F2806x_Headers_nonBIOS.cmd
========================================================= */
/* ======================================================
// For Code Composer Studio prior to V2.2
// --------------------------------------
// 1) Use one of the following -l statements to include the
// header linker command file in the project. The header linker
// file is required to link the peripheral structures to the proper
// locations within the memory map */
/* Uncomment this line to include file only for non-BIOS applications */
/* -l F2806x_Headers_nonBIOS.cmd */
/* Uncomment this line to include file only for BIOS applications */
/* -l F2806x_Headers_BIOS.cmd */
/* 2) In your project add the path to <base>\F2806x_headers\cmd to the
library search path under project->build options, linker tab,
library search path (-i).
/*========================================================= */
/* Define the memory block start/length for the F2806x
PAGE 0 will be used to organize program sections
PAGE 1 will be used to organize data sections
Notes:
Memory blocks on F28069 are uniform (ie same
physical memory) in both PAGE 0 and PAGE 1.
That is the same memory region should not be
defined for both PAGE 0 and PAGE 1.
Doing so will result in corruption of program
and/or data.
Contiguous SARAM memory blocks can be combined
if required to create a larger memory block.
*/
MEMORY
{
PAGE 0 : /* Program Memory */
/* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */
OTP : origin = 0x3D7800, length = 0x000400 /* on-chip OTP */
BL_FH : origin = 0x3D8000, length = 0x004000 /* on-chip FLASH for bootloader*/
CRC : origin = 0x3DC000, length = 0x000100
APP_FLASH : origin = 0x3DC100, length = 0x01BE80 /* on-chip FLASH for application*/
CSM_RSVD : origin = 0x3F7F80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */
BEGIN : origin = 0x3F7FF6, length = 0x000002 /* Part of FLASHA. Used for "boot to Flash" bootloader mode. */
CSM_PWL_P0 : origin = 0x3F7FF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */
FPUTABLES : origin = 0x3FD590, length = 0x0006A0 /* FPU Tables in Boot ROM */
IQTABLES : origin = 0x3FDC30, length = 0x000B50 /* IQ Math Tables in Boot ROM */
IQTABLES2 : origin = 0x3FE780, length = 0x00008C /* IQ Math Tables in Boot ROM */
IQTABLES3 : origin = 0x3FE80C, length = 0x0000AA /* IQ Math Tables in Boot ROM */
ROM : origin = 0x3FF3B0, length = 0x000C10 /* Boot ROM */
RESET : origin = 0x3FFFC0, length = 0x000002 /* part of boot ROM */
VECTORS : origin = 0x3FFFC2, length = 0x00003E /* part of boot ROM */
PAGE 1 : /* Data Memory */
/* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */
/* Registers remain on PAGE1 */
BOOT_RSVD : origin = 0x000000, length = 0x000050 /* Part of M0, BOOT rom will use this for stack */
PIEVECT : origin = 0xD00, length = 0x100
RAMM0_1 : origin = 0x000050, length = 0x0007B0 /* on-chip RAM block M0 */
RAM : origin = 0x008000, length = 0x003F00
STACK : origin = 0x00BF00, length = 0x001200
TASK_STACKS : origin = 0x00D100, length = 0x002C00
RAM_FUNCS : origin = 0x00FD00, length = 0x002300
USB_RAM : origin = 0x040000, length = 0x000800 /* USB RAM */
}
/* Allocate sections to memory blocks.
Note:
codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code
execution when booting to flash
ramfuncs user defined section to store functions that will be copied from Flash into RAM
*/
SECTIONS
{
bl_table : > 0x3D8000, PAGE = 0, type = DSECT
app_table : > CRC, PAGE = 0
.TI.ramfunc : {} LOAD=APP_FLASH PAGE = 0,
RUN=RAM_FUNCS PAGE = 1,
crc_table(_CRCTestVector),
TABLE(BINIT)
/* Allocate program areas: */
GROUP : > APP_FLASH, PAGE = 0, crc_table(_CRCTestVector,algorithm=CRC32_PRIME)
{
.cinit
.pinit
.binit
codestart
.text
/* Initalized sections to go in Flash */
/* For SDFlash to program these, they must be allocated to page 0 */
.econst
.switch
}
/* Allocate program areas: */
.TI.crctab : > CRC, PAGE = 0
csmpasswds : > CSM_PWL_P0, PAGE = 0
csm_rsvd : > CSM_RSVD, PAGE = 0
//.cinit : > APP_FLASH, PAGE = 0
//.binit : {} > APP_FLASH, PAGE = 0
//.pinit : > APP_FLASH, PAGE = 0
//.text : > APP_FLASH, PAGE = 0
//codestart : > BEGIN, PAGE = 0
//.TI.ramfunc : {} LOAD=APP_FLASH PAGE = 0,
// RUN=RAM_FUNCS PAGE = 1,
// TABLE(BINIT)
csmpasswds : > CSM_PWL_P0, PAGE = 0
csm_rsvd : > CSM_RSVD, PAGE = 0
/* Allocate uninitalized data sections: */
.stack : > STACK, PAGE = 1
.task_stack : > TASK_STACKS PAGE = 1
.ebss : > RAM, PAGE = 1
.esysmem : > RAM, PAGE = 1
// .cio buf is used by OS no real way around it
.cio : > RAM, PAGE = 1
/* Allocate IQ math areas: */
IQmath : > APP_FLASH, PAGE = 0 /* Math Code */
IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD
/* Allocate FPU math areas: */
FPUmathTables : > FPUTABLES, PAGE = 0, TYPE = NOLOAD
/* Uncomment the section below if calling the IQNexp() or IQexp()
functions from the IQMath.lib library in order to utilize the
relevant IQ Math table in Boot ROM (This saves space and Boot ROM
is 1 wait-state). If this section is not uncommented, IQmathTables2
will be loaded into other memory (SARAM, Flash, etc.) and will take
up space, but 0 wait-state is possible.
*/
/*
IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD
{
IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)
}
*/
/* Uncomment the section below if calling the IQNasin() or IQasin()
functions from the IQMath.lib library in order to utilize the
relevant IQ Math table in Boot ROM (This saves space and Boot ROM
is 1 wait-state). If this section is not uncommented, IQmathTables2
will be loaded into other memory (SARAM, Flash, etc.) and will take
up space, but 0 wait-state is possible.
*/
/*
IQmathTables3 : > IQTABLES3, PAGE = 0, TYPE = NOLOAD
{
IQmath.lib<IQNasinTable.obj> (IQmathTablesRam)
}
*/
/* .reset is a standard section used by the compiler. It contains the */
/* the address of the start of _c_int00 for C Code. /*
/* When using the boot ROM this section and the CPU vector */
/* table is not needed. Thus the default type is set here to */
/* DSECT */
.reset : > RESET, PAGE = 0, TYPE = DSECT
vectors : > VECTORS, PAGE = 0, TYPE = DSECT
}
/*
//===========================================================================
// End of file.
//===========================================================================
*/
and this is my bootloader linker file
/*
//###########################################################################
//
// FILE: F28069.cmd
//
// TITLE: Linker Command File For F28069 Device
//
//###########################################################################
// $TI Release: F2806x Support Library v2.04.00.00 $
// $Release Date: Mon May 27 06:46:38 CDT 2019 $
// $Copyright:
// Copyright (C) 2009-2019 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
*/
/* ======================================================
// For Code Composer Studio V2.2 and later
// ---------------------------------------
// In addition to this memory linker command file,
// add the header linker command file directly to the project.
// The header linker command file is required to link the
// peripheral structures to the proper locations within
// the memory map.
//
// The header linker files are found in <base>\headers\cmd
//
// For BIOS applications add: F2806x_Headers_BIOS.cmd
// For nonBIOS applications add: F2806x_Headers_nonBIOS.cmd
========================================================= */
/* ======================================================
// For Code Composer Studio prior to V2.2
// --------------------------------------
// 1) Use one of the following -l statements to include the
// header linker command file in the project. The header linker
// file is required to link the peripheral structures to the proper
// locations within the memory map */
/* Uncomment this line to include file only for non-BIOS applications */
/* -l F2806x_Headers_nonBIOS.cmd */
/* Uncomment this line to include file only for BIOS applications */
/* -l F2806x_Headers_BIOS.cmd */
/* 2) In your project add the path to <base>\headers\cmd to the
library search path under project->build options, linker tab,
library search path (-i).
/*========================================================= */
/* Define the memory block start/length for the F2806x
PAGE 0 will be used to organize program sections
PAGE 1 will be used to organize data sections
Notes:
Memory blocks on F28069 are uniform (ie same
physical memory) in both PAGE 0 and PAGE 1.
That is the same memory region should not be
defined for both PAGE 0 and PAGE 1.
Doing so will result in corruption of program
and/or data.
Contiguous SARAM memory blocks can be combined
if required to create a larger memory block.
*/
MEMORY
{
PAGE 0 : /* Program Memory */
/* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */
RAML01234 : origin = 0x008000, length = 0x004000 /* on-chip RAM block L0 */
OTP : origin = 0x3D7800, length = 0x000400 /* on-chip OTP */
BL_FH : origin = 0x3D8000, length = 0x004000 /* on-chip FLASH for bootloader*/
CRC : origin = 0x3DC000, length = 0x000100
APP_FLASH : origin = 0x3DC100, length = 0x01BE80 /* on-chip FLASH for application*/
CSM_RSVD : origin = 0x3F7F80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */
BEGIN : origin = 0x3F7FF6, length = 0x000002 /* Part of FLASHA. Used for "boot to Flash" bootloader mode. */
CSM_PWL_P0 : origin = 0x3F7FF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */
FPUTABLES : origin = 0x3FD860, length = 0x0006A0 /* FPU Tables in Boot ROM */
IQTABLES : origin = 0x3FDF00, length = 0x000B50 /* IQ Math Tables in Boot ROM */
IQTABLES2 : origin = 0x3FEA50, length = 0x00008C /* IQ Math Tables in Boot ROM */
IQTABLES3 : origin = 0x3FEADC, length = 0x0000AA /* IQ Math Tables in Boot ROM */
ROM : origin = 0x3FF3B0, length = 0x000C10 /* Boot ROM */
RESET : origin = 0x3FFFC0, length = 0x000002 /* part of boot ROM */
VECTORS : origin = 0x3FFFC2, length = 0x00003E /* part of boot ROM */
PAGE 1 : /* Data Memory */
/* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */
/* Registers remain on PAGE1 */
BOOT_RSVD : origin = 0x000000, length = 0x000050 /* Part of M0, BOOT rom will use this for stack */
RAMM0 : origin = 0x000050, length = 0x0003B0 /* on-chip RAM block M0 */
RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */
RAML5 : origin = 0x00C000, length = 0x002000 /* on-chip RAM block L5 */
RAML678 : origin = 0x00E000, length = 0x006000 /* on-chip RAM block L6 */
USB_RAM : origin = 0x040000, length = 0x000800 /* USB RAM */
FLASHB : origin = 0x3F0000, length = 0x004000 /* on-chip FLASH */
}
/* Allocate sections to memory blocks.
Note:
codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code
execution when booting to flash
ramfuncs user defined section to store functions that will be copied from Flash into RAM
*/
SECTIONS
{
/* Allocate program areas: */
bl_table : > BL_FH,
LOAD_START(_BLTableStart),
LOAD_END(_BLTableEnd),
LOAD_SIZE(_BLTableSize),
PAGE = 0
app_table : > CRC, PAGE = 0, type = DSECT
codestart : > BEGIN
GROUP : > BL_FH,
LOAD_START(_InitLoadStart),
LOAD_END(_InitLoadEnd),
LOAD_SIZE(_InitLoadSize),
PAGE = 0
{
codestart_n
.cinit
.pinit
normal
{ -l c28x_vcu0_library.lib(.text)}
}
GROUP : LOAD = BL_FH,
RUN = RAML01234,
LOAD_START(_RamfuncsLoadStart),
LOAD_END(_RamfuncsLoadEnd),
LOAD_SIZE(_RamfuncsLoadSize),
RUN_START(_RamfuncsRunStart)
{
.text
.econst
ramfuncs
}
GROUP : LOAD = BL_FH,
RUN = 0x3DE000,
LOAD_START(_FailsafeLoadStart),
LOAD_END(_FailsafeLoadEnd),
LOAD_SIZE(_FailsafeLoadSize),
RUN_START(_FailsafeRunStart),
PAGE = 0
{
codestart_f
failsafe
}
csmpasswds : > CSM_PWL_P0, PAGE = 0
csm_rsvd : > CSM_RSVD, PAGE = 0
/* Allocate uninitalized data sections: */
.stack : > RAMM1, PAGE = 1
.ebss : >> RAML5 | RAML678, PAGE = 1
.esysmem : >> RAML5, PAGE = 1
CRC32_TABLE : > RAML5, PAGE = 1
/* DMARAML6 : > RAML6, PAGE = 1 */
/* DMARAML7 : > RAML7, PAGE = 1 */
/* DMARAML8 : > RAML8, PAGE = 1 */
/* Uncomment the section below if calling the IQNexp() or IQexp()
functions from the IQMath.lib library in order to utilize the
relevant IQ Math table in Boot ROM (This saves space and Boot ROM
is 1 wait-state). If this section is not uncommented, IQmathTables2
will be loaded into other memory (SARAM, Flash, etc.) and will take
up space, but 0 wait-state is possible.
*/
/*
IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD
{
IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)
}
*/
/* Uncomment the section below if calling the IQNasin() or IQasin()
functions from the IQMath.lib library in order to utilize the
relevant IQ Math table in Boot ROM (This saves space and Boot ROM
is 1 wait-state). If this section is not uncommented, IQmathTables2
will be loaded into other memory (SARAM, Flash, etc.) and will take
up space, but 0 wait-state is possible.
*/
/*
IQmathTables3 : > IQTABLES3, PAGE = 0, TYPE = NOLOAD
{
IQmath.lib<IQNasinTable.obj> (IQmathTablesRam)
}
*/
/* .reset is a standard section used by the compiler. It contains the */
/* the address of the start of _c_int00 for C Code. /*
/* When using the boot ROM this section and the CPU vector */
/* table is not needed. Thus the default type is set here to */
/* DSECT */
.reset : > RESET, PAGE = 0, TYPE = DSECT
vectors : > VECTORS, PAGE = 0, TYPE = DSECT
}
/*
//===========================================================================
// End of file.
//===========================================================================
*/
Thanks
Nandini
