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Part Number: TMS320F28069M
Tool/software: Code Composer Studio
Hi!
I am trying to use the simultaneous sampling ADC mode in my DSP (F28069M), but something is wrong because it does not read the correct values. I follow the steps recommended in TMS320x2806x Piccolo Technical Reference Manual. Is there any code which I can compare my code? Can anyone explain the proccess (or way) followed by my sampled signal?
Very thanks for your time.
Best regards,
Álvaro
Alvaro,
Thanks for reaching out to the E2E forum.
I'm assuming that if you sample using sequential(non simultaneous) mode the ADC sample is correct? If so, please post your ADC setup code snippet that you have and I'll take a look at it for correctness.
One note about simultaneous mode is that it is only valid for an A/B channel pair; that is if the CHSEL = 1 and SMODE = 1 then the ADC will sample ADCINA1 and ADCINB1. There is no way to simultaneously sample 2 ADCINAx or 2 ADCINBx together.
Will look for your reply.
Best,
Matthew
I will attach my code. When I use the sequential mode it works nice. Both methods are in the same code. Sequential is commented.
Very thanks for your time!
//PICHICA, TIENES QEU ORDENAR EN STRUCTS: VER QEU VARIABLES GLOBALES Y CUALES GLOBALES
//PICHICA, TIENES QUE PONER TODO EN LECTURA SIMULATANEA
//LLEVAR LAS INTERRUPCIONES INT 1 Y 2 A GRUPO 10. USAR UN SOLO GRUPO
//ORDENAR SOCs. PRIMERO LOS DE LA CORRIENTE DE LA BOBINA, LUEGO LOS DE LA REFERENCIA
//###########################################################################
//
// FILE: Example_2806xAdcSoc.c
//
// TITLE: ADC Start of Conversion Example
//
//! \addtogroup f2806x_example_list
//! <h1> ADC Start of Conversion (adc_soc)</h1>
//!
//! This ADC example uses ePWM1 to generate a periodic ADC SOC - ADCINT1.
//! Two channels are converted, ADCINA4 and ADCINA2.
//!
//! \b Watch \b Variables \n
//! - Voltage1[10] - Last 10 ADCRESULT0 values
//! - Voltage2[10] - Last 10 ADCRESULT1 values
//! - ConversionCount - Current result number 0-9
//! - LoopCount - Idle loop counter
//
//###########################################################################
// $TI Release: F2806x Support Library v2.04.00.00 $
// $Release Date: Sun Sep 29 07:33:29 CDT 2019 $
// $Copyright:
// Copyright (C) 2009-2019 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
//
// Included Files
//
#include "DSP28x_Project.h" // Device Headerfile and Examples Include File
//
// Function Prototypes
//
__interrupt void adc_isr1(void);
__interrupt void adc_isr2(void);
__interrupt void adc_isr3(void);
void Adc_Config(void);
void InitEPwm1Example(void);
void InitEPwm2Example(void);
void InitEPwm3Example(void);
//
// Globals
//
Uint16 ConversionCount;
Uint16 Voltage;
Uint16 Voltagereferencia;
Uint32 EPwm1TimerIntCount;
Uint32 EPwm2TimerIntCount;
Uint32 EPwm3TimerIntCount;
#define EPWM1_MIN_DB 0x0064
#define EPWM2_MIN_DB 0x0064
#define EPWM3_MIN_DB 0x0064
float duty1 = 0.5;
float dutyold1=0;
float dutyoldold1=0;
float il1=0;
float ilold1=0;
float iloldold1=0;
float duty2 = 0.5;
float dutyold2=0;
float dutyoldold2=0;
float il2=0;
float ilold2=0;
float iloldold2=0;
float referencia=2330;
const int Offset=0;
float duty3 = 0.5;
float dutyold3=0;
float dutyoldold3=0;
float il3=0;
float ilold3=0;
float iloldold3=0;
//
// Main
//
void main(void)
{
//
// Step 1. Initialize System Control:
// PLL, WatchDog, enable Peripheral Clocks
// This example function is found in the F2806x_SysCtrl.c file.
//
InitSysCtrl();
//
// Step 2. Initialize GPIO:
// This example function is found in the F2806x_Gpio.c file and
// illustrates how to set the GPIO to it's default state.
//
//InitGpio(); // Skipped for this example
//Inicio pines para ver si da tiempo a c�lculos
EALLOW;
GpioCtrlRegs.GPAMUX1.bit.GPIO12=0x0000;
GpioCtrlRegs.GPAPUD.bit.GPIO12=0x0000;
GpioCtrlRegs.GPADIR.bit.GPIO12=0x0001;
GpioCtrlRegs.GPAQSEL1.bit.GPIO12=0x0000;
GpioCtrlRegs.GPAMUX2.bit.GPIO18=0x0000;
GpioCtrlRegs.GPAPUD.bit.GPIO18=0x0000;
GpioCtrlRegs.GPADIR.bit.GPIO18=0x0001;
GpioCtrlRegs.GPAQSEL2.bit.GPIO18=0x0000;
GpioCtrlRegs.GPAMUX2.bit.GPIO22=0x0000;
GpioCtrlRegs.GPAPUD.bit.GPIO22=0x0000;
GpioCtrlRegs.GPADIR.bit.GPIO22=0x0001;
GpioCtrlRegs.GPAQSEL2.bit.GPIO22=0x0000;
EDIS;
InitEPwm1Gpio();
InitEPwm2Gpio();
InitEPwm3Gpio();
//
// Step 3. Clear all interrupts and initialize PIE vector table:
// Disable CPU interrupts
//
DINT;
//
// Initialize the PIE control registers to their default state.
// The default state is all PIE interrupts disabled and flags
// are cleared.
// This function is found in the F2806x_PieCtrl.c file.
//
InitPieCtrl();
//
// Disable CPU interrupts and clear all CPU interrupt flags:
//
IER = 0x0000;
IFR = 0x0000;
//
// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
// This will populate the entire table, even if the interrupt
// is not used in this example. This is useful for debug purposes.
// The shell ISR routines are found in F2806x_DefaultIsr.c.
// This function is found in F2806x_PieVect.c.
//
InitPieVectTable();
//
// Interrupts that are used in this example are re-mapped to
// ISR functions found within this file.
//
EALLOW; // This is needed to write to EALLOW protected register
PieVectTable.ADCINT1 = &adc_isr1;
EDIS; // This is needed to disable write to EALLOW protected registers
EALLOW; // This is needed to write to EALLOW protected register
PieVectTable.ADCINT2 = &adc_isr2;
EDIS;
EALLOW; // This is needed to write to EALLOW protected register
PieVectTable.ADCINT3 = &adc_isr3;
EDIS;
//
// Step 4. Initialize all the Device Peripherals:
// This function is found in F2806x_InitPeripherals.c
// InitPeripherals(); // Not required for this example
//
InitAdc(); // For this example, init the ADC
AdcOffsetSelfCal();
//
// Step 5. User specific code, enable interrupts:
//
//
// Enable ADCINT1 in PIE
//
PieCtrlRegs.PIEIER1.bit.INTx1 = 1; // Enable INT 1.1 in the PIE
PieCtrlRegs.PIEIER1.bit.INTx2 = 1; // Enable INT 1.2 in the PIE
PieCtrlRegs.PIEIER10.bit.INTx3 = 1; // Enable INT 10.3 in the PIE
IER |= M_INT10; // Enable CPU Interrupt 1
IER |= M_INT1;
EINT; // Enable Global interrupt INTM
ERTM; // Enable Global realtime interrupt DBGM
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;
EDIS;
InitEPwm1Example();
InitEPwm2Example();
InitEPwm3Example();
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;
EDIS;
ConversionCount = 0;
EPwm1TimerIntCount = 0;
EPwm2TimerIntCount = 0;
EPwm3TimerIntCount = 0;
//
// Configure ADC
//
EALLOW;
AdcRegs.ADCCTL2.bit.ADCNONOVERLAP = 1; // Enable non-overlap mode
//
// ADCINT1 trips after AdcResults latch
//
AdcRegs.ADCCTL1.bit.INTPULSEPOS = 1;
AdcRegs.INTSEL1N2.bit.INT1E = 1; // Enabled ADCINT1
AdcRegs.INTSEL1N2.bit.INT1CONT = 0; // Disable ADCINT1 Continuous mode
AdcRegs.INTSEL1N2.bit.INT2E = 1; // Enabled ADCINT2
AdcRegs.INTSEL1N2.bit.INT2CONT = 0; // Disable ADCINT2 Continuous mode
AdcRegs.INTSEL3N4.bit.INT3E = 1; // Enabled ADCINT3
AdcRegs.INTSEL3N4.bit.INT3CONT = 0; // Disable ADCINT3 Continuous mode
//
// setup EOC1 to trigger ADCINT1 to fire
//
/* //SEQUENTIAL MODE
AdcRegs.INTSEL1N2.bit.INT1SEL = 1;
AdcRegs.INTSEL1N2.bit.INT2SEL = 1;
AdcRegs.INTSEL3N4.bit.INT3SEL = 1;
*/
//SIMULTANEOUS MODE
AdcRegs.ADCSAMPLEMODE.bit.SIMULEN0=1;
AdcRegs.ADCSOC0CTL.bit.CHSEL = 0;
AdcRegs.ADCSAMPLEMODE.bit.SIMULEN2=1;
AdcRegs.ADCSOC2CTL.bit.CHSEL = 1;
AdcRegs.ADCSAMPLEMODE.bit.SIMULEN4=1;
AdcRegs.ADCSOC4CTL.bit.CHSEL = 2;
/* //Sequential mode
AdcRegs.ADCSOC0CTL.bit.CHSEL = 0; // set SOC0 channel select to ADCINA0
AdcRegs.ADCSOC1CTL.bit.CHSEL = 8; // set SOC1 channel select to ADCINB0
AdcRegs.ADCSOC2CTL.bit.CHSEL = 1; // set SOC2 channel select to ADCINA1
AdcRegs.ADCSOC3CTL.bit.CHSEL = 9; // set SOC3 channel select to ADCINB1
AdcRegs.ADCSOC4CTL.bit.CHSEL = 2; // set SOC4 channel select to ADCINA2
AdcRegs.ADCSOC5CTL.bit.CHSEL = 0x000A; // set SOC5 channel select to ADCINB2
*/
//TUUUU SI ACTIVAS SIMULTANEO, QUITA SOC DE AQUI ABAJO, PON LOS TRIGGERS BIEN Y ADQS
// SIMULTANEOUS
AdcRegs.ADCSOC0CTL.bit.TRIGSEL = 5;
AdcRegs.ADCSOC2CTL.bit.TRIGSEL = 7;
AdcRegs.ADCSOC4CTL.bit.TRIGSEL = 9;
/*
//
//SEQUENTIAL
// set SOC0 start trigger on EPWM1A, due to round-robin SOC0 converts
// first then SOC1
//
AdcRegs.ADCSOC0CTL.bit.TRIGSEL = 5;
//
// set SOC1 start trigger on EPWM1A, due to round-robin SOC0 converts
// first then SOC1
//
AdcRegs.ADCSOC1CTL.bit.TRIGSEL = 5;
//
// set SOC2 start trigger on EPWM2A, due to round-robin SOC0 converts
// first then SOC1
//
AdcRegs.ADCSOC2CTL.bit.TRIGSEL = 7;
//
// set SOC3 start trigger on EPWM1A, due to round-robin SOC0 converts
// first then SOC1
//
AdcRegs.ADCSOC3CTL.bit.TRIGSEL = 7;
//
// set SOC4 start trigger on EPWM3A, due to round-robin SOC0 converts
// first then SOC1
//
AdcRegs.ADCSOC4CTL.bit.TRIGSEL = 9;
//
// set SOC5 start trigger on EPWM3A, due to round-robin SOC0 converts
// first then SOC1
//
AdcRegs.ADCSOC5CTL.bit.TRIGSEL = 9;
//
// set SOC0 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
//
AdcRegs.ADCSOC0CTL.bit.ACQPS = 6;
//
// set SOC1 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
//
AdcRegs.ADCSOC1CTL.bit.ACQPS = 6;
//
// set SOC0 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
//
AdcRegs.ADCSOC2CTL.bit.ACQPS = 6;
//
// set SOC1 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
//
AdcRegs.ADCSOC3CTL.bit.ACQPS = 6;
//
// set SOC0 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
//
AdcRegs.ADCSOC4CTL.bit.ACQPS = 6;
//
// set SOC1 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
//
AdcRegs.ADCSOC5CTL.bit.ACQPS = 6;
*/
// SIMULTANEUS
AdcRegs.ADCSOC0CTL.bit.ACQPS = 0x0028;
AdcRegs.ADCSOC2CTL.bit.ACQPS = 0x0028;
AdcRegs.ADCSOC4CTL.bit.ACQPS = 0x0028;
EDIS;
for(;;)
{
}
}
//
// adc_isr -
//
__interrupt void
adc_isr1(void)
{
GpioDataRegs.GPASET.bit.GPIO18=0x0001;
iloldold1=ilold1;
ilold1=il1;
il1 = (referencia-(AdcResult.ADCRESULT1-Offset))*0.00081;
//il1 = (AdcResult.ADCRESULT0-(AdcResult.ADCRESULT1-Offset))*0.00081; //Ojo que hay que a�adirle el offset a la entrada
dutyoldold1=dutyold1;
dutyold1=duty1;
duty1 = 0.0007876*il1+0.0001147*ilold1-0.0006729*iloldold1+0.1743*dutyold1+0.8257*dutyoldold1;
//duty1=0.0007876*il1+duty1;
if (duty1 < 0.1)
{
duty1 = 0.1;
}
if (duty1 > 0.9)
{
duty1 = 0.9;
}
EPwm1Regs.CMPA.half.CMPA = (Uint16)(duty1*1500);
EPwm1Regs.CMPB=(Uint16)(duty1*750+EPWM1_MIN_DB);
//
// Clear ADCINT1 flag reinitialize for next SOC
//
AdcRegs.ADCINTFLGCLR.bit.ADCINT1 = 1;
PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; // Acknowledge interrupt to PIE
GpioDataRegs.GPACLEAR.bit.GPIO18=0x0001;
return;
}
__interrupt void
adc_isr2(void)
{
GpioDataRegs.GPASET.bit.GPIO22=0x0001;
iloldold2=ilold2;
ilold2=il2;
il2 = (referencia-(AdcResult.ADCRESULT3-Offset))*0.00081;
//il2 = (AdcResult.ADCRESULT2-(AdcResult.ADCRESULT3-Offset))*0.00081;
dutyoldold2=dutyold2;
dutyold2=duty2;
duty2 = 0.0007876*il2+0.0001147*ilold2-0.0006729*iloldold2+0.1743*dutyold2+0.8257*dutyoldold2;
//duty=0.0007876*il+duty;
if (duty2 < 0.1)
{
duty2 = 0.1;
}
if (duty2 > 0.9)
{
duty2 = 0.9;
}
EPwm2Regs.CMPA.half.CMPA = (Uint16)(duty2*1500);
EPwm2Regs.CMPB=(Uint16)(duty2*750+EPWM2_MIN_DB);
//
// Clear ADCINT1 flag reinitialize for next SOC
//
AdcRegs.ADCINTFLGCLR.bit.ADCINT2 = 1;
PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; // Acknowledge interrupt to PIE
GpioDataRegs.GPACLEAR.bit.GPIO22=0x0001;
return;
}
__interrupt void
adc_isr3(void)
{
GpioDataRegs.GPASET.bit.GPIO12=0x0001;
iloldold3=ilold3;
ilold3=il3;
il3 = (referencia-(AdcResult.ADCRESULT5-Offset))*0.00081;
//il3 = (AdcResult.ADCRESULT4-(AdcResult.ADCRESULT5-Offset))*0.00081; //Ojo que hay que a�adirle el offset a la entrada
dutyoldold3=dutyold3;
dutyold3=duty3;
duty3 = 0.0007876*il3+0.0001147*ilold3-0.0006729*iloldold3+0.1743*dutyold3+0.8257*dutyoldold3;
//dut31=0.0007876*il3+duty3;
if (duty3 < 0.1)
{
duty3 = 0.1;
}
if (duty3 > 0.9)
{
duty3 = 0.9;
}
EPwm3Regs.CMPA.half.CMPA = (Uint16)(duty3*1500);
EPwm3Regs.CMPB=(Uint16)(duty3*750+EPWM3_MIN_DB);
//
// Clear ADCINT3 flag reinitialize for next SOC
//
AdcRegs.ADCINTFLGCLR.bit.ADCINT3 = 1;
PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; // Acknowledge interrupt to PIE grupo 10
GpioDataRegs.GPACLEAR.bit.GPIO12=0x0001;
return;
}
void
InitEPwm1Example()
{
//EN este caso, la salida 40 da 3.3 si duty es 0 y 0 si duty es 1
EPwm1Regs.ETSEL.bit.SOCAEN = 1; // Enable SOC on A group
EPwm1Regs.ETSEL.bit.SOCASEL = 6; // Select SOC from CMPB on upcount
EPwm1Regs.ETPS.bit.SOCAPRD = 1; // Generate pulse on 1st event
EPwm1Regs.TBPRD = 1499; // Set timer period
EPwm1Regs.TBPHS.half.TBPHS = 0x0000; // Phase is a 0
EPwm1Regs.TBCTR = 0x0000; // Clear counter
//
// Setup TBCLK
//
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load registers every ZERO
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
//
// Setup compare
//
EPwm1Regs.CMPA.half.CMPA = duty1*1500;
EPwm1Regs.CMPB=750+EPWM1_MIN_DB;
//
// Set actions
//
EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Set PWM1A on CAU
EPwm1Regs.AQCTLA.bit.ZRO = AQ_SET; // Clear PWM1A on CAD
EPwm1Regs.AQCTLB.bit.CAU = AQ_SET; // Clear PWM1B on CAU
EPwm1Regs.AQCTLB.bit.ZRO = AQ_CLEAR; // Set PWM1B on CAD
//
// Active Low PWMs - Setup Deadband
//
EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
EPwm1Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm1Regs.DBRED = EPWM1_MIN_DB;
EPwm1Regs.DBFED = EPWM1_MIN_DB;
}
void
InitEPwm2Example()
{
EPwm2Regs.ETSEL.bit.SOCAEN = 1; // Enable SOC on A group
EPwm2Regs.ETSEL.bit.SOCASEL = 6; // Select SOC from CMPB on upcount
EPwm2Regs.ETPS.bit.SOCAPRD = 1; // Generate pulse on 1st event
EPwm2Regs.TBPRD = 1499; // Set timer period
EPwm2Regs.TBPHS.half.TBPHS = 500; // Phase is 0
EPwm2Regs.TBCTR = 0x0000; // Clear counter
//
// Setup TBCLK
//
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up
EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Disable phase loading
EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load registers every ZERO
EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
//
// Setup compare
//
EPwm2Regs.CMPA.half.CMPA = duty2*1500;
EPwm2Regs.CMPB=750+EPWM2_MIN_DB;
//
// Set actions
//
EPwm2Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Set PWM1A on CAU
EPwm2Regs.AQCTLA.bit.ZRO = AQ_SET; // Clear PWM1A on CAD
EPwm2Regs.AQCTLB.bit.CAU = AQ_SET; // Clear PWM1B on CAU
EPwm2Regs.AQCTLB.bit.ZRO = AQ_CLEAR; // Set PWM1B on CAD
//
// Active Low PWMs - Setup Deadband
//
EPwm2Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
EPwm2Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm2Regs.DBRED = EPWM2_MIN_DB;
EPwm2Regs.DBFED = EPWM2_MIN_DB;
//EPwm2_DB_Direction = DB_UP;
/*
//
// Interrupt where we will change the Deadband
//
EPwm2Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm2Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm2Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event
*/
}
//
// InitEPwm3Example -
//
void
InitEPwm3Example()
{
EPwm3Regs.ETSEL.bit.SOCAEN = 1; // Enable SOC on A group
EPwm3Regs.ETSEL.bit.SOCASEL = 6; // Select SOC from CMPB on upcount
EPwm3Regs.ETPS.bit.SOCAPRD = 1; // Generate pulse on 1st event
EPwm3Regs.TBPRD = 1499; // Set timer period
EPwm3Regs.TBPHS.half.TBPHS = 1000; // Phase is 0
EPwm3Regs.TBCTR = 0x0000; // Clear counter
//
// Setup TBCLK
//
EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up
EPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Disable phase loading
EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm3Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load registers every ZERO
EPwm3Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm3Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
//
// Setup compare
//
EPwm3Regs.CMPA.half.CMPA = duty3*1500;
EPwm3Regs.CMPB=750+EPWM3_MIN_DB;
//
// Set actions
//
EPwm3Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Set PWM1A on CAU
EPwm3Regs.AQCTLA.bit.ZRO = AQ_SET; // Clear PWM1A on CAD
EPwm3Regs.AQCTLB.bit.CAU = AQ_SET; // Clear PWM1B on CAU
EPwm3Regs.AQCTLB.bit.ZRO = AQ_CLEAR; // Set PWM1B on CAD
//
// Active Low PWMs - Setup Deadband
//
EPwm3Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm3Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
EPwm3Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm3Regs.DBRED = EPWM3_MIN_DB;
EPwm3Regs.DBFED = EPWM3_MIN_DB;
/*
//
// Interrupt where we will change the deadband
//
EPwm3Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm3Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm3Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event
*/
}
//
// End of File
//
Alvaro,
I'm attached three modified .c files per the following:
1)6082.Example_2806xAdcSoc_INTSEL.c - try this first, in simultaneous mode I didn't see where you were confguring the source EOC for the ADCINT1/2/3 so I added that. If this was the issue then all 3 ISRs would be triggered by EOC0, which would happen after the SOC0 conversion is finished
2)6082.Example_2806xAdcSoc_INTSEL_dis_odd.c - in this code I'm making sure that the trigger is dis-abled for the odd SOCs, which could cause an extra sample to occur in addition to the above(in case you are debugging simul/sequential modes back to back)
3)6082.Example_2806xAdcSoc_INTSEL_dis_odd_ACQPS1.c - all the above, but I've increased the S/H window by 1 to see if this improves your results
Best,
Matthew
//PICHICA, TIENES QEU ORDENAR EN STRUCTS: VER QEU VARIABLES GLOBALES Y CUALES GLOBALES
//PICHICA, TIENES QUE PONER TODO EN LECTURA SIMULATANEA
//LLEVAR LAS INTERRUPCIONES INT 1 Y 2 A GRUPO 10. USAR UN SOLO GRUPO
//ORDENAR SOCs. PRIMERO LOS DE LA CORRIENTE DE LA BOBINA, LUEGO LOS DE LA REFERENCIA
//###########################################################################
//
// FILE: Example_2806xAdcSoc.c
//
// TITLE: ADC Start of Conversion Example
//
//! \addtogroup f2806x_example_list
//! <h1> ADC Start of Conversion (adc_soc)</h1>
//!
//! This ADC example uses ePWM1 to generate a periodic ADC SOC - ADCINT1.
//! Two channels are converted, ADCINA4 and ADCINA2.
//!
//! \b Watch \b Variables \n
//! - Voltage1[10] - Last 10 ADCRESULT0 values
//! - Voltage2[10] - Last 10 ADCRESULT1 values
//! - ConversionCount - Current result number 0-9
//! - LoopCount - Idle loop counter
//
//###########################################################################
// $TI Release: F2806x Support Library v2.04.00.00 $
// $Release Date: Sun Sep 29 07:33:29 CDT 2019 $
// $Copyright:
// Copyright (C) 2009-2019 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
//
// Included Files
//
#include "DSP28x_Project.h" // Device Headerfile and Examples Include File
//
// Function Prototypes
//
__interrupt void adc_isr1(void);
__interrupt void adc_isr2(void);
__interrupt void adc_isr3(void);
void Adc_Config(void);
void InitEPwm1Example(void);
void InitEPwm2Example(void);
void InitEPwm3Example(void);
//
// Globals
//
Uint16 ConversionCount;
Uint16 Voltage;
Uint16 Voltagereferencia;
Uint32 EPwm1TimerIntCount;
Uint32 EPwm2TimerIntCount;
Uint32 EPwm3TimerIntCount;
#define EPWM1_MIN_DB 0x0064
#define EPWM2_MIN_DB 0x0064
#define EPWM3_MIN_DB 0x0064
float duty1 = 0.5;
float dutyold1=0;
float dutyoldold1=0;
float il1=0;
float ilold1=0;
float iloldold1=0;
float duty2 = 0.5;
float dutyold2=0;
float dutyoldold2=0;
float il2=0;
float ilold2=0;
float iloldold2=0;
float referencia=2330;
const int Offset=0;
float duty3 = 0.5;
float dutyold3=0;
float dutyoldold3=0;
float il3=0;
float ilold3=0;
float iloldold3=0;
//
// Main
//
void main(void)
{
//
// Step 1. Initialize System Control:
// PLL, WatchDog, enable Peripheral Clocks
// This example function is found in the F2806x_SysCtrl.c file.
//
InitSysCtrl();
//
// Step 2. Initialize GPIO:
// This example function is found in the F2806x_Gpio.c file and
// illustrates how to set the GPIO to it's default state.
//
//InitGpio(); // Skipped for this example
//Inicio pines para ver si da tiempo a c�lculos
EALLOW;
GpioCtrlRegs.GPAMUX1.bit.GPIO12=0x0000;
GpioCtrlRegs.GPAPUD.bit.GPIO12=0x0000;
GpioCtrlRegs.GPADIR.bit.GPIO12=0x0001;
GpioCtrlRegs.GPAQSEL1.bit.GPIO12=0x0000;
GpioCtrlRegs.GPAMUX2.bit.GPIO18=0x0000;
GpioCtrlRegs.GPAPUD.bit.GPIO18=0x0000;
GpioCtrlRegs.GPADIR.bit.GPIO18=0x0001;
GpioCtrlRegs.GPAQSEL2.bit.GPIO18=0x0000;
GpioCtrlRegs.GPAMUX2.bit.GPIO22=0x0000;
GpioCtrlRegs.GPAPUD.bit.GPIO22=0x0000;
GpioCtrlRegs.GPADIR.bit.GPIO22=0x0001;
GpioCtrlRegs.GPAQSEL2.bit.GPIO22=0x0000;
EDIS;
InitEPwm1Gpio();
InitEPwm2Gpio();
InitEPwm3Gpio();
//
// Step 3. Clear all interrupts and initialize PIE vector table:
// Disable CPU interrupts
//
DINT;
//
// Initialize the PIE control registers to their default state.
// The default state is all PIE interrupts disabled and flags
// are cleared.
// This function is found in the F2806x_PieCtrl.c file.
//
InitPieCtrl();
//
// Disable CPU interrupts and clear all CPU interrupt flags:
//
IER = 0x0000;
IFR = 0x0000;
//
// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
// This will populate the entire table, even if the interrupt
// is not used in this example. This is useful for debug purposes.
// The shell ISR routines are found in F2806x_DefaultIsr.c.
// This function is found in F2806x_PieVect.c.
//
InitPieVectTable();
//
// Interrupts that are used in this example are re-mapped to
// ISR functions found within this file.
//
EALLOW; // This is needed to write to EALLOW protected register
PieVectTable.ADCINT1 = &adc_isr1;
EDIS; // This is needed to disable write to EALLOW protected registers
EALLOW; // This is needed to write to EALLOW protected register
PieVectTable.ADCINT2 = &adc_isr2;
EDIS;
EALLOW; // This is needed to write to EALLOW protected register
PieVectTable.ADCINT3 = &adc_isr3;
EDIS;
//
// Step 4. Initialize all the Device Peripherals:
// This function is found in F2806x_InitPeripherals.c
// InitPeripherals(); // Not required for this example
//
InitAdc(); // For this example, init the ADC
AdcOffsetSelfCal();
//
// Step 5. User specific code, enable interrupts:
//
//
// Enable ADCINT1 in PIE
//
PieCtrlRegs.PIEIER1.bit.INTx1 = 1; // Enable INT 1.1 in the PIE
PieCtrlRegs.PIEIER1.bit.INTx2 = 1; // Enable INT 1.2 in the PIE
PieCtrlRegs.PIEIER10.bit.INTx3 = 1; // Enable INT 10.3 in the PIE
IER |= M_INT10; // Enable CPU Interrupt 1
IER |= M_INT1;
EINT; // Enable Global interrupt INTM
ERTM; // Enable Global realtime interrupt DBGM
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;
EDIS;
InitEPwm1Example();
InitEPwm2Example();
InitEPwm3Example();
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;
EDIS;
ConversionCount = 0;
EPwm1TimerIntCount = 0;
EPwm2TimerIntCount = 0;
EPwm3TimerIntCount = 0;
//
// Configure ADC
//
EALLOW;
AdcRegs.ADCCTL2.bit.ADCNONOVERLAP = 1; // Enable non-overlap mode
//
// ADCINT1 trips after AdcResults latch
//
AdcRegs.ADCCTL1.bit.INTPULSEPOS = 1;
AdcRegs.INTSEL1N2.bit.INT1E = 1; // Enabled ADCINT1
AdcRegs.INTSEL1N2.bit.INT1CONT = 0; // Disable ADCINT1 Continuous mode
AdcRegs.INTSEL1N2.bit.INT1SEL = 1; // EOC1 triggers INT1
AdcRegs.INTSEL1N2.bit.INT2E = 1; // Enabled ADCINT2
AdcRegs.INTSEL1N2.bit.INT2CONT = 0; // Disable ADCINT2 Continuous mode
AdcRegs.INTSEL1N2.bit.INT2SEL = 3; // EOC3 triggers INT2
AdcRegs.INTSEL3N4.bit.INT3E = 1; // Enabled ADCINT3
AdcRegs.INTSEL3N4.bit.INT3CONT = 0; // Disable ADCINT3 Continuous mode
AdcRegs.INTSEL3N4.bit.INT3SEL = 5; // EOC5 triggers INT3
//
// setup EOC1 to trigger ADCINT1 to fire
//
/* //SEQUENTIAL MODE
AdcRegs.INTSEL1N2.bit.INT1SEL = 1;
AdcRegs.INTSEL1N2.bit.INT2SEL = 1;
AdcRegs.INTSEL3N4.bit.INT3SEL = 1;
*/
//SIMULTANEOUS MODE
AdcRegs.ADCSAMPLEMODE.bit.SIMULEN0=1;
AdcRegs.ADCSOC0CTL.bit.CHSEL = 0;
AdcRegs.ADCSAMPLEMODE.bit.SIMULEN2=1;
AdcRegs.ADCSOC2CTL.bit.CHSEL = 1;
AdcRegs.ADCSAMPLEMODE.bit.SIMULEN4=1;
AdcRegs.ADCSOC4CTL.bit.CHSEL = 2;
/* //Sequential mode
AdcRegs.ADCSOC0CTL.bit.CHSEL = 0; // set SOC0 channel select to ADCINA0
AdcRegs.ADCSOC1CTL.bit.CHSEL = 8; // set SOC1 channel select to ADCINB0
AdcRegs.ADCSOC2CTL.bit.CHSEL = 1; // set SOC2 channel select to ADCINA1
AdcRegs.ADCSOC3CTL.bit.CHSEL = 9; // set SOC3 channel select to ADCINB1
AdcRegs.ADCSOC4CTL.bit.CHSEL = 2; // set SOC4 channel select to ADCINA2
AdcRegs.ADCSOC5CTL.bit.CHSEL = 0x000A; // set SOC5 channel select to ADCINB2
*/
//TUUUU SI ACTIVAS SIMULTANEO, QUITA SOC DE AQUI ABAJO, PON LOS TRIGGERS BIEN Y ADQS
// SIMULTANEOUS
AdcRegs.ADCSOC0CTL.bit.TRIGSEL = 5;
// AdcRegs.ADCSOC1CTL.bit.TRIGSEL = 0; //make sure that the odd SOCs are disabled.
AdcRegs.ADCSOC2CTL.bit.TRIGSEL = 7;
// AdcRegs.ADCSOC3CTL.bit.TRIGSEL = 0;
AdcRegs.ADCSOC4CTL.bit.TRIGSEL = 9;
// AdcRegs.ADCSOC5CTL.bit.TRIGSEL = 0;
/*
//
//SEQUENTIAL
// set SOC0 start trigger on EPWM1A, due to round-robin SOC0 converts
// first then SOC1
//
AdcRegs.ADCSOC0CTL.bit.TRIGSEL = 5;
//
// set SOC1 start trigger on EPWM1A, due to round-robin SOC0 converts
// first then SOC1
//
AdcRegs.ADCSOC1CTL.bit.TRIGSEL = 5;
//
// set SOC2 start trigger on EPWM2A, due to round-robin SOC0 converts
// first then SOC1
//
AdcRegs.ADCSOC2CTL.bit.TRIGSEL = 7;
//
// set SOC3 start trigger on EPWM1A, due to round-robin SOC0 converts
// first then SOC1
//
AdcRegs.ADCSOC3CTL.bit.TRIGSEL = 7;
//
// set SOC4 start trigger on EPWM3A, due to round-robin SOC0 converts
// first then SOC1
//
AdcRegs.ADCSOC4CTL.bit.TRIGSEL = 9;
//
// set SOC5 start trigger on EPWM3A, due to round-robin SOC0 converts
// first then SOC1
//
AdcRegs.ADCSOC5CTL.bit.TRIGSEL = 9;
//
// set SOC0 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
//
AdcRegs.ADCSOC0CTL.bit.ACQPS = 6;
//
// set SOC1 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
//
AdcRegs.ADCSOC1CTL.bit.ACQPS = 6;
//
// set SOC0 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
//
AdcRegs.ADCSOC2CTL.bit.ACQPS = 6;
//
// set SOC1 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
//
AdcRegs.ADCSOC3CTL.bit.ACQPS = 6;
//
// set SOC0 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
//
AdcRegs.ADCSOC4CTL.bit.ACQPS = 6;
//
// set SOC1 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
//
AdcRegs.ADCSOC5CTL.bit.ACQPS = 6;
*/
// SIMULTANEUS
AdcRegs.ADCSOC0CTL.bit.ACQPS = 0x0028;
AdcRegs.ADCSOC2CTL.bit.ACQPS = 0x0028;
AdcRegs.ADCSOC4CTL.bit.ACQPS = 0x0028;
EDIS;
for(;;)
{
}
}
//
// adc_isr -
//
__interrupt void
adc_isr1(void)
{
GpioDataRegs.GPASET.bit.GPIO18=0x0001;
iloldold1=ilold1;
ilold1=il1;
il1 = (referencia-(AdcResult.ADCRESULT1-Offset))*0.00081;
//il1 = (AdcResult.ADCRESULT0-(AdcResult.ADCRESULT1-Offset))*0.00081; //Ojo que hay que a�adirle el offset a la entrada
dutyoldold1=dutyold1;
dutyold1=duty1;
duty1 = 0.0007876*il1+0.0001147*ilold1-0.0006729*iloldold1+0.1743*dutyold1+0.8257*dutyoldold1;
//duty1=0.0007876*il1+duty1;
if (duty1 < 0.1)
{
duty1 = 0.1;
}
if (duty1 > 0.9)
{
duty1 = 0.9;
}
EPwm1Regs.CMPA.half.CMPA = (Uint16)(duty1*1500);
EPwm1Regs.CMPB=(Uint16)(duty1*750+EPWM1_MIN_DB);
//
// Clear ADCINT1 flag reinitialize for next SOC
//
AdcRegs.ADCINTFLGCLR.bit.ADCINT1 = 1;
PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; // Acknowledge interrupt to PIE
GpioDataRegs.GPACLEAR.bit.GPIO18=0x0001;
return;
}
__interrupt void
adc_isr2(void)
{
GpioDataRegs.GPASET.bit.GPIO22=0x0001;
iloldold2=ilold2;
ilold2=il2;
il2 = (referencia-(AdcResult.ADCRESULT3-Offset))*0.00081;
//il2 = (AdcResult.ADCRESULT2-(AdcResult.ADCRESULT3-Offset))*0.00081;
dutyoldold2=dutyold2;
dutyold2=duty2;
duty2 = 0.0007876*il2+0.0001147*ilold2-0.0006729*iloldold2+0.1743*dutyold2+0.8257*dutyoldold2;
//duty=0.0007876*il+duty;
if (duty2 < 0.1)
{
duty2 = 0.1;
}
if (duty2 > 0.9)
{
duty2 = 0.9;
}
EPwm2Regs.CMPA.half.CMPA = (Uint16)(duty2*1500);
EPwm2Regs.CMPB=(Uint16)(duty2*750+EPWM2_MIN_DB);
//
// Clear ADCINT1 flag reinitialize for next SOC
//
AdcRegs.ADCINTFLGCLR.bit.ADCINT2 = 1;
PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; // Acknowledge interrupt to PIE
GpioDataRegs.GPACLEAR.bit.GPIO22=0x0001;
return;
}
__interrupt void
adc_isr3(void)
{
GpioDataRegs.GPASET.bit.GPIO12=0x0001;
iloldold3=ilold3;
ilold3=il3;
il3 = (referencia-(AdcResult.ADCRESULT5-Offset))*0.00081;
//il3 = (AdcResult.ADCRESULT4-(AdcResult.ADCRESULT5-Offset))*0.00081; //Ojo que hay que a�adirle el offset a la entrada
dutyoldold3=dutyold3;
dutyold3=duty3;
duty3 = 0.0007876*il3+0.0001147*ilold3-0.0006729*iloldold3+0.1743*dutyold3+0.8257*dutyoldold3;
//dut31=0.0007876*il3+duty3;
if (duty3 < 0.1)
{
duty3 = 0.1;
}
if (duty3 > 0.9)
{
duty3 = 0.9;
}
EPwm3Regs.CMPA.half.CMPA = (Uint16)(duty3*1500);
EPwm3Regs.CMPB=(Uint16)(duty3*750+EPWM3_MIN_DB);
//
// Clear ADCINT3 flag reinitialize for next SOC
//
AdcRegs.ADCINTFLGCLR.bit.ADCINT3 = 1;
PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; // Acknowledge interrupt to PIE grupo 10
GpioDataRegs.GPACLEAR.bit.GPIO12=0x0001;
return;
}
void
InitEPwm1Example()
{
//EN este caso, la salida 40 da 3.3 si duty es 0 y 0 si duty es 1
EPwm1Regs.ETSEL.bit.SOCAEN = 1; // Enable SOC on A group
EPwm1Regs.ETSEL.bit.SOCASEL = 6; // Select SOC from CMPB on upcount
EPwm1Regs.ETPS.bit.SOCAPRD = 1; // Generate pulse on 1st event
EPwm1Regs.TBPRD = 1499; // Set timer period
EPwm1Regs.TBPHS.half.TBPHS = 0x0000; // Phase is a 0
EPwm1Regs.TBCTR = 0x0000; // Clear counter
//
// Setup TBCLK
//
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load registers every ZERO
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
//
// Setup compare
//
EPwm1Regs.CMPA.half.CMPA = duty1*1500;
EPwm1Regs.CMPB=750+EPWM1_MIN_DB;
//
// Set actions
//
EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Set PWM1A on CAU
EPwm1Regs.AQCTLA.bit.ZRO = AQ_SET; // Clear PWM1A on CAD
EPwm1Regs.AQCTLB.bit.CAU = AQ_SET; // Clear PWM1B on CAU
EPwm1Regs.AQCTLB.bit.ZRO = AQ_CLEAR; // Set PWM1B on CAD
//
// Active Low PWMs - Setup Deadband
//
EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
EPwm1Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm1Regs.DBRED = EPWM1_MIN_DB;
EPwm1Regs.DBFED = EPWM1_MIN_DB;
}
void
InitEPwm2Example()
{
EPwm2Regs.ETSEL.bit.SOCAEN = 1; // Enable SOC on A group
EPwm2Regs.ETSEL.bit.SOCASEL = 6; // Select SOC from CMPB on upcount
EPwm2Regs.ETPS.bit.SOCAPRD = 1; // Generate pulse on 1st event
EPwm2Regs.TBPRD = 1499; // Set timer period
EPwm2Regs.TBPHS.half.TBPHS = 500; // Phase is 0
EPwm2Regs.TBCTR = 0x0000; // Clear counter
//
// Setup TBCLK
//
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up
EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Disable phase loading
EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load registers every ZERO
EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
//
// Setup compare
//
EPwm2Regs.CMPA.half.CMPA = duty2*1500;
EPwm2Regs.CMPB=750+EPWM2_MIN_DB;
//
// Set actions
//
EPwm2Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Set PWM1A on CAU
EPwm2Regs.AQCTLA.bit.ZRO = AQ_SET; // Clear PWM1A on CAD
EPwm2Regs.AQCTLB.bit.CAU = AQ_SET; // Clear PWM1B on CAU
EPwm2Regs.AQCTLB.bit.ZRO = AQ_CLEAR; // Set PWM1B on CAD
//
// Active Low PWMs - Setup Deadband
//
EPwm2Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
EPwm2Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm2Regs.DBRED = EPWM2_MIN_DB;
EPwm2Regs.DBFED = EPWM2_MIN_DB;
//EPwm2_DB_Direction = DB_UP;
/*
//
// Interrupt where we will change the Deadband
//
EPwm2Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm2Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm2Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event
*/
}
//
// InitEPwm3Example -
//
void
InitEPwm3Example()
{
EPwm3Regs.ETSEL.bit.SOCAEN = 1; // Enable SOC on A group
EPwm3Regs.ETSEL.bit.SOCASEL = 6; // Select SOC from CMPB on upcount
EPwm3Regs.ETPS.bit.SOCAPRD = 1; // Generate pulse on 1st event
EPwm3Regs.TBPRD = 1499; // Set timer period
EPwm3Regs.TBPHS.half.TBPHS = 1000; // Phase is 0
EPwm3Regs.TBCTR = 0x0000; // Clear counter
//
// Setup TBCLK
//
EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up
EPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Disable phase loading
EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm3Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load registers every ZERO
EPwm3Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm3Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
//
// Setup compare
//
EPwm3Regs.CMPA.half.CMPA = duty3*1500;
EPwm3Regs.CMPB=750+EPWM3_MIN_DB;
//
// Set actions
//
EPwm3Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Set PWM1A on CAU
EPwm3Regs.AQCTLA.bit.ZRO = AQ_SET; // Clear PWM1A on CAD
EPwm3Regs.AQCTLB.bit.CAU = AQ_SET; // Clear PWM1B on CAU
EPwm3Regs.AQCTLB.bit.ZRO = AQ_CLEAR; // Set PWM1B on CAD
//
// Active Low PWMs - Setup Deadband
//
EPwm3Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm3Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
EPwm3Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm3Regs.DBRED = EPWM3_MIN_DB;
EPwm3Regs.DBFED = EPWM3_MIN_DB;
/*
//
// Interrupt where we will change the deadband
//
EPwm3Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm3Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm3Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event
*/
}
//
// End of File
//
//PICHICA, TIENES QEU ORDENAR EN STRUCTS: VER QEU VARIABLES GLOBALES Y CUALES GLOBALES
//PICHICA, TIENES QUE PONER TODO EN LECTURA SIMULATANEA
//LLEVAR LAS INTERRUPCIONES INT 1 Y 2 A GRUPO 10. USAR UN SOLO GRUPO
//ORDENAR SOCs. PRIMERO LOS DE LA CORRIENTE DE LA BOBINA, LUEGO LOS DE LA REFERENCIA
//###########################################################################
//
// FILE: Example_2806xAdcSoc.c
//
// TITLE: ADC Start of Conversion Example
//
//! \addtogroup f2806x_example_list
//! <h1> ADC Start of Conversion (adc_soc)</h1>
//!
//! This ADC example uses ePWM1 to generate a periodic ADC SOC - ADCINT1.
//! Two channels are converted, ADCINA4 and ADCINA2.
//!
//! \b Watch \b Variables \n
//! - Voltage1[10] - Last 10 ADCRESULT0 values
//! - Voltage2[10] - Last 10 ADCRESULT1 values
//! - ConversionCount - Current result number 0-9
//! - LoopCount - Idle loop counter
//
//###########################################################################
// $TI Release: F2806x Support Library v2.04.00.00 $
// $Release Date: Sun Sep 29 07:33:29 CDT 2019 $
// $Copyright:
// Copyright (C) 2009-2019 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
//
// Included Files
//
#include "DSP28x_Project.h" // Device Headerfile and Examples Include File
//
// Function Prototypes
//
__interrupt void adc_isr1(void);
__interrupt void adc_isr2(void);
__interrupt void adc_isr3(void);
void Adc_Config(void);
void InitEPwm1Example(void);
void InitEPwm2Example(void);
void InitEPwm3Example(void);
//
// Globals
//
Uint16 ConversionCount;
Uint16 Voltage;
Uint16 Voltagereferencia;
Uint32 EPwm1TimerIntCount;
Uint32 EPwm2TimerIntCount;
Uint32 EPwm3TimerIntCount;
#define EPWM1_MIN_DB 0x0064
#define EPWM2_MIN_DB 0x0064
#define EPWM3_MIN_DB 0x0064
float duty1 = 0.5;
float dutyold1=0;
float dutyoldold1=0;
float il1=0;
float ilold1=0;
float iloldold1=0;
float duty2 = 0.5;
float dutyold2=0;
float dutyoldold2=0;
float il2=0;
float ilold2=0;
float iloldold2=0;
float referencia=2330;
const int Offset=0;
float duty3 = 0.5;
float dutyold3=0;
float dutyoldold3=0;
float il3=0;
float ilold3=0;
float iloldold3=0;
//
// Main
//
void main(void)
{
//
// Step 1. Initialize System Control:
// PLL, WatchDog, enable Peripheral Clocks
// This example function is found in the F2806x_SysCtrl.c file.
//
InitSysCtrl();
//
// Step 2. Initialize GPIO:
// This example function is found in the F2806x_Gpio.c file and
// illustrates how to set the GPIO to it's default state.
//
//InitGpio(); // Skipped for this example
//Inicio pines para ver si da tiempo a c�lculos
EALLOW;
GpioCtrlRegs.GPAMUX1.bit.GPIO12=0x0000;
GpioCtrlRegs.GPAPUD.bit.GPIO12=0x0000;
GpioCtrlRegs.GPADIR.bit.GPIO12=0x0001;
GpioCtrlRegs.GPAQSEL1.bit.GPIO12=0x0000;
GpioCtrlRegs.GPAMUX2.bit.GPIO18=0x0000;
GpioCtrlRegs.GPAPUD.bit.GPIO18=0x0000;
GpioCtrlRegs.GPADIR.bit.GPIO18=0x0001;
GpioCtrlRegs.GPAQSEL2.bit.GPIO18=0x0000;
GpioCtrlRegs.GPAMUX2.bit.GPIO22=0x0000;
GpioCtrlRegs.GPAPUD.bit.GPIO22=0x0000;
GpioCtrlRegs.GPADIR.bit.GPIO22=0x0001;
GpioCtrlRegs.GPAQSEL2.bit.GPIO22=0x0000;
EDIS;
InitEPwm1Gpio();
InitEPwm2Gpio();
InitEPwm3Gpio();
//
// Step 3. Clear all interrupts and initialize PIE vector table:
// Disable CPU interrupts
//
DINT;
//
// Initialize the PIE control registers to their default state.
// The default state is all PIE interrupts disabled and flags
// are cleared.
// This function is found in the F2806x_PieCtrl.c file.
//
InitPieCtrl();
//
// Disable CPU interrupts and clear all CPU interrupt flags:
//
IER = 0x0000;
IFR = 0x0000;
//
// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
// This will populate the entire table, even if the interrupt
// is not used in this example. This is useful for debug purposes.
// The shell ISR routines are found in F2806x_DefaultIsr.c.
// This function is found in F2806x_PieVect.c.
//
InitPieVectTable();
//
// Interrupts that are used in this example are re-mapped to
// ISR functions found within this file.
//
EALLOW; // This is needed to write to EALLOW protected register
PieVectTable.ADCINT1 = &adc_isr1;
EDIS; // This is needed to disable write to EALLOW protected registers
EALLOW; // This is needed to write to EALLOW protected register
PieVectTable.ADCINT2 = &adc_isr2;
EDIS;
EALLOW; // This is needed to write to EALLOW protected register
PieVectTable.ADCINT3 = &adc_isr3;
EDIS;
//
// Step 4. Initialize all the Device Peripherals:
// This function is found in F2806x_InitPeripherals.c
// InitPeripherals(); // Not required for this example
//
InitAdc(); // For this example, init the ADC
AdcOffsetSelfCal();
//
// Step 5. User specific code, enable interrupts:
//
//
// Enable ADCINT1 in PIE
//
PieCtrlRegs.PIEIER1.bit.INTx1 = 1; // Enable INT 1.1 in the PIE
PieCtrlRegs.PIEIER1.bit.INTx2 = 1; // Enable INT 1.2 in the PIE
PieCtrlRegs.PIEIER10.bit.INTx3 = 1; // Enable INT 10.3 in the PIE
IER |= M_INT10; // Enable CPU Interrupt 1
IER |= M_INT1;
EINT; // Enable Global interrupt INTM
ERTM; // Enable Global realtime interrupt DBGM
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;
EDIS;
InitEPwm1Example();
InitEPwm2Example();
InitEPwm3Example();
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;
EDIS;
ConversionCount = 0;
EPwm1TimerIntCount = 0;
EPwm2TimerIntCount = 0;
EPwm3TimerIntCount = 0;
//
// Configure ADC
//
EALLOW;
AdcRegs.ADCCTL2.bit.ADCNONOVERLAP = 1; // Enable non-overlap mode
//
// ADCINT1 trips after AdcResults latch
//
AdcRegs.ADCCTL1.bit.INTPULSEPOS = 1;
AdcRegs.INTSEL1N2.bit.INT1E = 1; // Enabled ADCINT1
AdcRegs.INTSEL1N2.bit.INT1CONT = 0; // Disable ADCINT1 Continuous mode
AdcRegs.INTSEL1N2.bit.INT1SEL = 1; // EOC1 triggers INT1
AdcRegs.INTSEL1N2.bit.INT2E = 1; // Enabled ADCINT2
AdcRegs.INTSEL1N2.bit.INT2CONT = 0; // Disable ADCINT2 Continuous mode
AdcRegs.INTSEL1N2.bit.INT2SEL = 3; // EOC3 triggers INT2
AdcRegs.INTSEL3N4.bit.INT3E = 1; // Enabled ADCINT3
AdcRegs.INTSEL3N4.bit.INT3CONT = 0; // Disable ADCINT3 Continuous mode
AdcRegs.INTSEL3N4.bit.INT3SEL = 5; // EOC5 triggers INT3
//
// setup EOC1 to trigger ADCINT1 to fire
//
/* //SEQUENTIAL MODE
AdcRegs.INTSEL1N2.bit.INT1SEL = 1;
AdcRegs.INTSEL1N2.bit.INT2SEL = 1;
AdcRegs.INTSEL3N4.bit.INT3SEL = 1;
*/
//SIMULTANEOUS MODE
AdcRegs.ADCSAMPLEMODE.bit.SIMULEN0=1;
AdcRegs.ADCSOC0CTL.bit.CHSEL = 0;
AdcRegs.ADCSAMPLEMODE.bit.SIMULEN2=1;
AdcRegs.ADCSOC2CTL.bit.CHSEL = 1;
AdcRegs.ADCSAMPLEMODE.bit.SIMULEN4=1;
AdcRegs.ADCSOC4CTL.bit.CHSEL = 2;
/* //Sequential mode
AdcRegs.ADCSOC0CTL.bit.CHSEL = 0; // set SOC0 channel select to ADCINA0
AdcRegs.ADCSOC1CTL.bit.CHSEL = 8; // set SOC1 channel select to ADCINB0
AdcRegs.ADCSOC2CTL.bit.CHSEL = 1; // set SOC2 channel select to ADCINA1
AdcRegs.ADCSOC3CTL.bit.CHSEL = 9; // set SOC3 channel select to ADCINB1
AdcRegs.ADCSOC4CTL.bit.CHSEL = 2; // set SOC4 channel select to ADCINA2
AdcRegs.ADCSOC5CTL.bit.CHSEL = 0x000A; // set SOC5 channel select to ADCINB2
*/
//TUUUU SI ACTIVAS SIMULTANEO, QUITA SOC DE AQUI ABAJO, PON LOS TRIGGERS BIEN Y ADQS
// SIMULTANEOUS
AdcRegs.ADCSOC0CTL.bit.TRIGSEL = 5;
AdcRegs.ADCSOC1CTL.bit.TRIGSEL = 0; //make sure that the odd SOCs are disabled.
AdcRegs.ADCSOC2CTL.bit.TRIGSEL = 7;
AdcRegs.ADCSOC3CTL.bit.TRIGSEL = 0;
AdcRegs.ADCSOC4CTL.bit.TRIGSEL = 9;
AdcRegs.ADCSOC5CTL.bit.TRIGSEL = 0;
/*
//
//SEQUENTIAL
// set SOC0 start trigger on EPWM1A, due to round-robin SOC0 converts
// first then SOC1
//
AdcRegs.ADCSOC0CTL.bit.TRIGSEL = 5;
//
// set SOC1 start trigger on EPWM1A, due to round-robin SOC0 converts
// first then SOC1
//
AdcRegs.ADCSOC1CTL.bit.TRIGSEL = 5;
//
// set SOC2 start trigger on EPWM2A, due to round-robin SOC0 converts
// first then SOC1
//
AdcRegs.ADCSOC2CTL.bit.TRIGSEL = 7;
//
// set SOC3 start trigger on EPWM1A, due to round-robin SOC0 converts
// first then SOC1
//
AdcRegs.ADCSOC3CTL.bit.TRIGSEL = 7;
//
// set SOC4 start trigger on EPWM3A, due to round-robin SOC0 converts
// first then SOC1
//
AdcRegs.ADCSOC4CTL.bit.TRIGSEL = 9;
//
// set SOC5 start trigger on EPWM3A, due to round-robin SOC0 converts
// first then SOC1
//
AdcRegs.ADCSOC5CTL.bit.TRIGSEL = 9;
//
// set SOC0 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
//
AdcRegs.ADCSOC0CTL.bit.ACQPS = 6;
//
// set SOC1 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
//
AdcRegs.ADCSOC1CTL.bit.ACQPS = 6;
//
// set SOC0 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
//
AdcRegs.ADCSOC2CTL.bit.ACQPS = 6;
//
// set SOC1 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
//
AdcRegs.ADCSOC3CTL.bit.ACQPS = 6;
//
// set SOC0 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
//
AdcRegs.ADCSOC4CTL.bit.ACQPS = 6;
//
// set SOC1 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
//
AdcRegs.ADCSOC5CTL.bit.ACQPS = 6;
*/
// SIMULTANEUS
AdcRegs.ADCSOC0CTL.bit.ACQPS = 0x0028;
AdcRegs.ADCSOC2CTL.bit.ACQPS = 0x0028;
AdcRegs.ADCSOC4CTL.bit.ACQPS = 0x0028;
EDIS;
for(;;)
{
}
}
//
// adc_isr -
//
__interrupt void
adc_isr1(void)
{
GpioDataRegs.GPASET.bit.GPIO18=0x0001;
iloldold1=ilold1;
ilold1=il1;
il1 = (referencia-(AdcResult.ADCRESULT1-Offset))*0.00081;
//il1 = (AdcResult.ADCRESULT0-(AdcResult.ADCRESULT1-Offset))*0.00081; //Ojo que hay que a�adirle el offset a la entrada
dutyoldold1=dutyold1;
dutyold1=duty1;
duty1 = 0.0007876*il1+0.0001147*ilold1-0.0006729*iloldold1+0.1743*dutyold1+0.8257*dutyoldold1;
//duty1=0.0007876*il1+duty1;
if (duty1 < 0.1)
{
duty1 = 0.1;
}
if (duty1 > 0.9)
{
duty1 = 0.9;
}
EPwm1Regs.CMPA.half.CMPA = (Uint16)(duty1*1500);
EPwm1Regs.CMPB=(Uint16)(duty1*750+EPWM1_MIN_DB);
//
// Clear ADCINT1 flag reinitialize for next SOC
//
AdcRegs.ADCINTFLGCLR.bit.ADCINT1 = 1;
PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; // Acknowledge interrupt to PIE
GpioDataRegs.GPACLEAR.bit.GPIO18=0x0001;
return;
}
__interrupt void
adc_isr2(void)
{
GpioDataRegs.GPASET.bit.GPIO22=0x0001;
iloldold2=ilold2;
ilold2=il2;
il2 = (referencia-(AdcResult.ADCRESULT3-Offset))*0.00081;
//il2 = (AdcResult.ADCRESULT2-(AdcResult.ADCRESULT3-Offset))*0.00081;
dutyoldold2=dutyold2;
dutyold2=duty2;
duty2 = 0.0007876*il2+0.0001147*ilold2-0.0006729*iloldold2+0.1743*dutyold2+0.8257*dutyoldold2;
//duty=0.0007876*il+duty;
if (duty2 < 0.1)
{
duty2 = 0.1;
}
if (duty2 > 0.9)
{
duty2 = 0.9;
}
EPwm2Regs.CMPA.half.CMPA = (Uint16)(duty2*1500);
EPwm2Regs.CMPB=(Uint16)(duty2*750+EPWM2_MIN_DB);
//
// Clear ADCINT1 flag reinitialize for next SOC
//
AdcRegs.ADCINTFLGCLR.bit.ADCINT2 = 1;
PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; // Acknowledge interrupt to PIE
GpioDataRegs.GPACLEAR.bit.GPIO22=0x0001;
return;
}
__interrupt void
adc_isr3(void)
{
GpioDataRegs.GPASET.bit.GPIO12=0x0001;
iloldold3=ilold3;
ilold3=il3;
il3 = (referencia-(AdcResult.ADCRESULT5-Offset))*0.00081;
//il3 = (AdcResult.ADCRESULT4-(AdcResult.ADCRESULT5-Offset))*0.00081; //Ojo que hay que a�adirle el offset a la entrada
dutyoldold3=dutyold3;
dutyold3=duty3;
duty3 = 0.0007876*il3+0.0001147*ilold3-0.0006729*iloldold3+0.1743*dutyold3+0.8257*dutyoldold3;
//dut31=0.0007876*il3+duty3;
if (duty3 < 0.1)
{
duty3 = 0.1;
}
if (duty3 > 0.9)
{
duty3 = 0.9;
}
EPwm3Regs.CMPA.half.CMPA = (Uint16)(duty3*1500);
EPwm3Regs.CMPB=(Uint16)(duty3*750+EPWM3_MIN_DB);
//
// Clear ADCINT3 flag reinitialize for next SOC
//
AdcRegs.ADCINTFLGCLR.bit.ADCINT3 = 1;
PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; // Acknowledge interrupt to PIE grupo 10
GpioDataRegs.GPACLEAR.bit.GPIO12=0x0001;
return;
}
void
InitEPwm1Example()
{
//EN este caso, la salida 40 da 3.3 si duty es 0 y 0 si duty es 1
EPwm1Regs.ETSEL.bit.SOCAEN = 1; // Enable SOC on A group
EPwm1Regs.ETSEL.bit.SOCASEL = 6; // Select SOC from CMPB on upcount
EPwm1Regs.ETPS.bit.SOCAPRD = 1; // Generate pulse on 1st event
EPwm1Regs.TBPRD = 1499; // Set timer period
EPwm1Regs.TBPHS.half.TBPHS = 0x0000; // Phase is a 0
EPwm1Regs.TBCTR = 0x0000; // Clear counter
//
// Setup TBCLK
//
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load registers every ZERO
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
//
// Setup compare
//
EPwm1Regs.CMPA.half.CMPA = duty1*1500;
EPwm1Regs.CMPB=750+EPWM1_MIN_DB;
//
// Set actions
//
EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Set PWM1A on CAU
EPwm1Regs.AQCTLA.bit.ZRO = AQ_SET; // Clear PWM1A on CAD
EPwm1Regs.AQCTLB.bit.CAU = AQ_SET; // Clear PWM1B on CAU
EPwm1Regs.AQCTLB.bit.ZRO = AQ_CLEAR; // Set PWM1B on CAD
//
// Active Low PWMs - Setup Deadband
//
EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
EPwm1Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm1Regs.DBRED = EPWM1_MIN_DB;
EPwm1Regs.DBFED = EPWM1_MIN_DB;
}
void
InitEPwm2Example()
{
EPwm2Regs.ETSEL.bit.SOCAEN = 1; // Enable SOC on A group
EPwm2Regs.ETSEL.bit.SOCASEL = 6; // Select SOC from CMPB on upcount
EPwm2Regs.ETPS.bit.SOCAPRD = 1; // Generate pulse on 1st event
EPwm2Regs.TBPRD = 1499; // Set timer period
EPwm2Regs.TBPHS.half.TBPHS = 500; // Phase is 0
EPwm2Regs.TBCTR = 0x0000; // Clear counter
//
// Setup TBCLK
//
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up
EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Disable phase loading
EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load registers every ZERO
EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
//
// Setup compare
//
EPwm2Regs.CMPA.half.CMPA = duty2*1500;
EPwm2Regs.CMPB=750+EPWM2_MIN_DB;
//
// Set actions
//
EPwm2Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Set PWM1A on CAU
EPwm2Regs.AQCTLA.bit.ZRO = AQ_SET; // Clear PWM1A on CAD
EPwm2Regs.AQCTLB.bit.CAU = AQ_SET; // Clear PWM1B on CAU
EPwm2Regs.AQCTLB.bit.ZRO = AQ_CLEAR; // Set PWM1B on CAD
//
// Active Low PWMs - Setup Deadband
//
EPwm2Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
EPwm2Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm2Regs.DBRED = EPWM2_MIN_DB;
EPwm2Regs.DBFED = EPWM2_MIN_DB;
//EPwm2_DB_Direction = DB_UP;
/*
//
// Interrupt where we will change the Deadband
//
EPwm2Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm2Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm2Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event
*/
}
//
// InitEPwm3Example -
//
void
InitEPwm3Example()
{
EPwm3Regs.ETSEL.bit.SOCAEN = 1; // Enable SOC on A group
EPwm3Regs.ETSEL.bit.SOCASEL = 6; // Select SOC from CMPB on upcount
EPwm3Regs.ETPS.bit.SOCAPRD = 1; // Generate pulse on 1st event
EPwm3Regs.TBPRD = 1499; // Set timer period
EPwm3Regs.TBPHS.half.TBPHS = 1000; // Phase is 0
EPwm3Regs.TBCTR = 0x0000; // Clear counter
//
// Setup TBCLK
//
EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up
EPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Disable phase loading
EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm3Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load registers every ZERO
EPwm3Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm3Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
//
// Setup compare
//
EPwm3Regs.CMPA.half.CMPA = duty3*1500;
EPwm3Regs.CMPB=750+EPWM3_MIN_DB;
//
// Set actions
//
EPwm3Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Set PWM1A on CAU
EPwm3Regs.AQCTLA.bit.ZRO = AQ_SET; // Clear PWM1A on CAD
EPwm3Regs.AQCTLB.bit.CAU = AQ_SET; // Clear PWM1B on CAU
EPwm3Regs.AQCTLB.bit.ZRO = AQ_CLEAR; // Set PWM1B on CAD
//
// Active Low PWMs - Setup Deadband
//
EPwm3Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm3Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
EPwm3Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm3Regs.DBRED = EPWM3_MIN_DB;
EPwm3Regs.DBFED = EPWM3_MIN_DB;
/*
//
// Interrupt where we will change the deadband
//
EPwm3Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm3Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm3Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event
*/
}
//
// End of File
//
//PICHICA, TIENES QEU ORDENAR EN STRUCTS: VER QEU VARIABLES GLOBALES Y CUALES GLOBALES
//PICHICA, TIENES QUE PONER TODO EN LECTURA SIMULATANEA
//LLEVAR LAS INTERRUPCIONES INT 1 Y 2 A GRUPO 10. USAR UN SOLO GRUPO
//ORDENAR SOCs. PRIMERO LOS DE LA CORRIENTE DE LA BOBINA, LUEGO LOS DE LA REFERENCIA
//###########################################################################
//
// FILE: Example_2806xAdcSoc.c
//
// TITLE: ADC Start of Conversion Example
//
//! \addtogroup f2806x_example_list
//! <h1> ADC Start of Conversion (adc_soc)</h1>
//!
//! This ADC example uses ePWM1 to generate a periodic ADC SOC - ADCINT1.
//! Two channels are converted, ADCINA4 and ADCINA2.
//!
//! \b Watch \b Variables \n
//! - Voltage1[10] - Last 10 ADCRESULT0 values
//! - Voltage2[10] - Last 10 ADCRESULT1 values
//! - ConversionCount - Current result number 0-9
//! - LoopCount - Idle loop counter
//
//###########################################################################
// $TI Release: F2806x Support Library v2.04.00.00 $
// $Release Date: Sun Sep 29 07:33:29 CDT 2019 $
// $Copyright:
// Copyright (C) 2009-2019 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
//
// Included Files
//
#include "DSP28x_Project.h" // Device Headerfile and Examples Include File
//
// Function Prototypes
//
__interrupt void adc_isr1(void);
__interrupt void adc_isr2(void);
__interrupt void adc_isr3(void);
void Adc_Config(void);
void InitEPwm1Example(void);
void InitEPwm2Example(void);
void InitEPwm3Example(void);
//
// Globals
//
Uint16 ConversionCount;
Uint16 Voltage;
Uint16 Voltagereferencia;
Uint32 EPwm1TimerIntCount;
Uint32 EPwm2TimerIntCount;
Uint32 EPwm3TimerIntCount;
#define EPWM1_MIN_DB 0x0064
#define EPWM2_MIN_DB 0x0064
#define EPWM3_MIN_DB 0x0064
float duty1 = 0.5;
float dutyold1=0;
float dutyoldold1=0;
float il1=0;
float ilold1=0;
float iloldold1=0;
float duty2 = 0.5;
float dutyold2=0;
float dutyoldold2=0;
float il2=0;
float ilold2=0;
float iloldold2=0;
float referencia=2330;
const int Offset=0;
float duty3 = 0.5;
float dutyold3=0;
float dutyoldold3=0;
float il3=0;
float ilold3=0;
float iloldold3=0;
//
// Main
//
void main(void)
{
//
// Step 1. Initialize System Control:
// PLL, WatchDog, enable Peripheral Clocks
// This example function is found in the F2806x_SysCtrl.c file.
//
InitSysCtrl();
//
// Step 2. Initialize GPIO:
// This example function is found in the F2806x_Gpio.c file and
// illustrates how to set the GPIO to it's default state.
//
//InitGpio(); // Skipped for this example
//Inicio pines para ver si da tiempo a c�lculos
EALLOW;
GpioCtrlRegs.GPAMUX1.bit.GPIO12=0x0000;
GpioCtrlRegs.GPAPUD.bit.GPIO12=0x0000;
GpioCtrlRegs.GPADIR.bit.GPIO12=0x0001;
GpioCtrlRegs.GPAQSEL1.bit.GPIO12=0x0000;
GpioCtrlRegs.GPAMUX2.bit.GPIO18=0x0000;
GpioCtrlRegs.GPAPUD.bit.GPIO18=0x0000;
GpioCtrlRegs.GPADIR.bit.GPIO18=0x0001;
GpioCtrlRegs.GPAQSEL2.bit.GPIO18=0x0000;
GpioCtrlRegs.GPAMUX2.bit.GPIO22=0x0000;
GpioCtrlRegs.GPAPUD.bit.GPIO22=0x0000;
GpioCtrlRegs.GPADIR.bit.GPIO22=0x0001;
GpioCtrlRegs.GPAQSEL2.bit.GPIO22=0x0000;
EDIS;
InitEPwm1Gpio();
InitEPwm2Gpio();
InitEPwm3Gpio();
//
// Step 3. Clear all interrupts and initialize PIE vector table:
// Disable CPU interrupts
//
DINT;
//
// Initialize the PIE control registers to their default state.
// The default state is all PIE interrupts disabled and flags
// are cleared.
// This function is found in the F2806x_PieCtrl.c file.
//
InitPieCtrl();
//
// Disable CPU interrupts and clear all CPU interrupt flags:
//
IER = 0x0000;
IFR = 0x0000;
//
// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
// This will populate the entire table, even if the interrupt
// is not used in this example. This is useful for debug purposes.
// The shell ISR routines are found in F2806x_DefaultIsr.c.
// This function is found in F2806x_PieVect.c.
//
InitPieVectTable();
//
// Interrupts that are used in this example are re-mapped to
// ISR functions found within this file.
//
EALLOW; // This is needed to write to EALLOW protected register
PieVectTable.ADCINT1 = &adc_isr1;
EDIS; // This is needed to disable write to EALLOW protected registers
EALLOW; // This is needed to write to EALLOW protected register
PieVectTable.ADCINT2 = &adc_isr2;
EDIS;
EALLOW; // This is needed to write to EALLOW protected register
PieVectTable.ADCINT3 = &adc_isr3;
EDIS;
//
// Step 4. Initialize all the Device Peripherals:
// This function is found in F2806x_InitPeripherals.c
// InitPeripherals(); // Not required for this example
//
InitAdc(); // For this example, init the ADC
AdcOffsetSelfCal();
//
// Step 5. User specific code, enable interrupts:
//
//
// Enable ADCINT1 in PIE
//
PieCtrlRegs.PIEIER1.bit.INTx1 = 1; // Enable INT 1.1 in the PIE
PieCtrlRegs.PIEIER1.bit.INTx2 = 1; // Enable INT 1.2 in the PIE
PieCtrlRegs.PIEIER10.bit.INTx3 = 1; // Enable INT 10.3 in the PIE
IER |= M_INT10; // Enable CPU Interrupt 1
IER |= M_INT1;
EINT; // Enable Global interrupt INTM
ERTM; // Enable Global realtime interrupt DBGM
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;
EDIS;
InitEPwm1Example();
InitEPwm2Example();
InitEPwm3Example();
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;
EDIS;
ConversionCount = 0;
EPwm1TimerIntCount = 0;
EPwm2TimerIntCount = 0;
EPwm3TimerIntCount = 0;
//
// Configure ADC
//
EALLOW;
AdcRegs.ADCCTL2.bit.ADCNONOVERLAP = 1; // Enable non-overlap mode
//
// ADCINT1 trips after AdcResults latch
//
AdcRegs.ADCCTL1.bit.INTPULSEPOS = 1;
AdcRegs.INTSEL1N2.bit.INT1E = 1; // Enabled ADCINT1
AdcRegs.INTSEL1N2.bit.INT1CONT = 0; // Disable ADCINT1 Continuous mode
AdcRegs.INTSEL1N2.bit.INT1SEL = 1; // EOC1 triggers INT1
AdcRegs.INTSEL1N2.bit.INT2E = 1; // Enabled ADCINT2
AdcRegs.INTSEL1N2.bit.INT2CONT = 0; // Disable ADCINT2 Continuous mode
AdcRegs.INTSEL1N2.bit.INT2SEL = 3; // EOC3 triggers INT2
AdcRegs.INTSEL3N4.bit.INT3E = 1; // Enabled ADCINT3
AdcRegs.INTSEL3N4.bit.INT3CONT = 0; // Disable ADCINT3 Continuous mode
AdcRegs.INTSEL3N4.bit.INT3SEL = 5; // EOC5 triggers INT3
//
// setup EOC1 to trigger ADCINT1 to fire
//
/* //SEQUENTIAL MODE
AdcRegs.INTSEL1N2.bit.INT1SEL = 1;
AdcRegs.INTSEL1N2.bit.INT2SEL = 1;
AdcRegs.INTSEL3N4.bit.INT3SEL = 1;
*/
//SIMULTANEOUS MODE
AdcRegs.ADCSAMPLEMODE.bit.SIMULEN0=1;
AdcRegs.ADCSOC0CTL.bit.CHSEL = 0;
AdcRegs.ADCSAMPLEMODE.bit.SIMULEN2=1;
AdcRegs.ADCSOC2CTL.bit.CHSEL = 1;
AdcRegs.ADCSAMPLEMODE.bit.SIMULEN4=1;
AdcRegs.ADCSOC4CTL.bit.CHSEL = 2;
/* //Sequential mode
AdcRegs.ADCSOC0CTL.bit.CHSEL = 0; // set SOC0 channel select to ADCINA0
AdcRegs.ADCSOC1CTL.bit.CHSEL = 8; // set SOC1 channel select to ADCINB0
AdcRegs.ADCSOC2CTL.bit.CHSEL = 1; // set SOC2 channel select to ADCINA1
AdcRegs.ADCSOC3CTL.bit.CHSEL = 9; // set SOC3 channel select to ADCINB1
AdcRegs.ADCSOC4CTL.bit.CHSEL = 2; // set SOC4 channel select to ADCINA2
AdcRegs.ADCSOC5CTL.bit.CHSEL = 0x000A; // set SOC5 channel select to ADCINB2
*/
//TUUUU SI ACTIVAS SIMULTANEO, QUITA SOC DE AQUI ABAJO, PON LOS TRIGGERS BIEN Y ADQS
// SIMULTANEOUS
AdcRegs.ADCSOC0CTL.bit.TRIGSEL = 5;
AdcRegs.ADCSOC1CTL.bit.TRIGSEL = 0; //make sure that the odd SOCs are disabled.
AdcRegs.ADCSOC2CTL.bit.TRIGSEL = 7;
AdcRegs.ADCSOC3CTL.bit.TRIGSEL = 0;
AdcRegs.ADCSOC4CTL.bit.TRIGSEL = 9;
AdcRegs.ADCSOC5CTL.bit.TRIGSEL = 0;
/*
//
//SEQUENTIAL
// set SOC0 start trigger on EPWM1A, due to round-robin SOC0 converts
// first then SOC1
//
AdcRegs.ADCSOC0CTL.bit.TRIGSEL = 5;
//
// set SOC1 start trigger on EPWM1A, due to round-robin SOC0 converts
// first then SOC1
//
AdcRegs.ADCSOC1CTL.bit.TRIGSEL = 5;
//
// set SOC2 start trigger on EPWM2A, due to round-robin SOC0 converts
// first then SOC1
//
AdcRegs.ADCSOC2CTL.bit.TRIGSEL = 7;
//
// set SOC3 start trigger on EPWM1A, due to round-robin SOC0 converts
// first then SOC1
//
AdcRegs.ADCSOC3CTL.bit.TRIGSEL = 7;
//
// set SOC4 start trigger on EPWM3A, due to round-robin SOC0 converts
// first then SOC1
//
AdcRegs.ADCSOC4CTL.bit.TRIGSEL = 9;
//
// set SOC5 start trigger on EPWM3A, due to round-robin SOC0 converts
// first then SOC1
//
AdcRegs.ADCSOC5CTL.bit.TRIGSEL = 9;
//
// set SOC0 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
//
AdcRegs.ADCSOC0CTL.bit.ACQPS = 6;
//
// set SOC1 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
//
AdcRegs.ADCSOC1CTL.bit.ACQPS = 6;
//
// set SOC0 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
//
AdcRegs.ADCSOC2CTL.bit.ACQPS = 6;
//
// set SOC1 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
//
AdcRegs.ADCSOC3CTL.bit.ACQPS = 6;
//
// set SOC0 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
//
AdcRegs.ADCSOC4CTL.bit.ACQPS = 6;
//
// set SOC1 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
//
AdcRegs.ADCSOC5CTL.bit.ACQPS = 6;
*/
// SIMULTANEUS
AdcRegs.ADCSOC0CTL.bit.ACQPS = 0x0029;
AdcRegs.ADCSOC2CTL.bit.ACQPS = 0x0029;
AdcRegs.ADCSOC4CTL.bit.ACQPS = 0x0029;
EDIS;
for(;;)
{
}
}
//
// adc_isr -
//
__interrupt void
adc_isr1(void)
{
GpioDataRegs.GPASET.bit.GPIO18=0x0001;
iloldold1=ilold1;
ilold1=il1;
il1 = (referencia-(AdcResult.ADCRESULT1-Offset))*0.00081;
//il1 = (AdcResult.ADCRESULT0-(AdcResult.ADCRESULT1-Offset))*0.00081; //Ojo que hay que a�adirle el offset a la entrada
dutyoldold1=dutyold1;
dutyold1=duty1;
duty1 = 0.0007876*il1+0.0001147*ilold1-0.0006729*iloldold1+0.1743*dutyold1+0.8257*dutyoldold1;
//duty1=0.0007876*il1+duty1;
if (duty1 < 0.1)
{
duty1 = 0.1;
}
if (duty1 > 0.9)
{
duty1 = 0.9;
}
EPwm1Regs.CMPA.half.CMPA = (Uint16)(duty1*1500);
EPwm1Regs.CMPB=(Uint16)(duty1*750+EPWM1_MIN_DB);
//
// Clear ADCINT1 flag reinitialize for next SOC
//
AdcRegs.ADCINTFLGCLR.bit.ADCINT1 = 1;
PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; // Acknowledge interrupt to PIE
GpioDataRegs.GPACLEAR.bit.GPIO18=0x0001;
return;
}
__interrupt void
adc_isr2(void)
{
GpioDataRegs.GPASET.bit.GPIO22=0x0001;
iloldold2=ilold2;
ilold2=il2;
il2 = (referencia-(AdcResult.ADCRESULT3-Offset))*0.00081;
//il2 = (AdcResult.ADCRESULT2-(AdcResult.ADCRESULT3-Offset))*0.00081;
dutyoldold2=dutyold2;
dutyold2=duty2;
duty2 = 0.0007876*il2+0.0001147*ilold2-0.0006729*iloldold2+0.1743*dutyold2+0.8257*dutyoldold2;
//duty=0.0007876*il+duty;
if (duty2 < 0.1)
{
duty2 = 0.1;
}
if (duty2 > 0.9)
{
duty2 = 0.9;
}
EPwm2Regs.CMPA.half.CMPA = (Uint16)(duty2*1500);
EPwm2Regs.CMPB=(Uint16)(duty2*750+EPWM2_MIN_DB);
//
// Clear ADCINT1 flag reinitialize for next SOC
//
AdcRegs.ADCINTFLGCLR.bit.ADCINT2 = 1;
PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; // Acknowledge interrupt to PIE
GpioDataRegs.GPACLEAR.bit.GPIO22=0x0001;
return;
}
__interrupt void
adc_isr3(void)
{
GpioDataRegs.GPASET.bit.GPIO12=0x0001;
iloldold3=ilold3;
ilold3=il3;
il3 = (referencia-(AdcResult.ADCRESULT5-Offset))*0.00081;
//il3 = (AdcResult.ADCRESULT4-(AdcResult.ADCRESULT5-Offset))*0.00081; //Ojo que hay que a�adirle el offset a la entrada
dutyoldold3=dutyold3;
dutyold3=duty3;
duty3 = 0.0007876*il3+0.0001147*ilold3-0.0006729*iloldold3+0.1743*dutyold3+0.8257*dutyoldold3;
//dut31=0.0007876*il3+duty3;
if (duty3 < 0.1)
{
duty3 = 0.1;
}
if (duty3 > 0.9)
{
duty3 = 0.9;
}
EPwm3Regs.CMPA.half.CMPA = (Uint16)(duty3*1500);
EPwm3Regs.CMPB=(Uint16)(duty3*750+EPWM3_MIN_DB);
//
// Clear ADCINT3 flag reinitialize for next SOC
//
AdcRegs.ADCINTFLGCLR.bit.ADCINT3 = 1;
PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; // Acknowledge interrupt to PIE grupo 10
GpioDataRegs.GPACLEAR.bit.GPIO12=0x0001;
return;
}
void
InitEPwm1Example()
{
//EN este caso, la salida 40 da 3.3 si duty es 0 y 0 si duty es 1
EPwm1Regs.ETSEL.bit.SOCAEN = 1; // Enable SOC on A group
EPwm1Regs.ETSEL.bit.SOCASEL = 6; // Select SOC from CMPB on upcount
EPwm1Regs.ETPS.bit.SOCAPRD = 1; // Generate pulse on 1st event
EPwm1Regs.TBPRD = 1499; // Set timer period
EPwm1Regs.TBPHS.half.TBPHS = 0x0000; // Phase is a 0
EPwm1Regs.TBCTR = 0x0000; // Clear counter
//
// Setup TBCLK
//
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load registers every ZERO
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
//
// Setup compare
//
EPwm1Regs.CMPA.half.CMPA = duty1*1500;
EPwm1Regs.CMPB=750+EPWM1_MIN_DB;
//
// Set actions
//
EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Set PWM1A on CAU
EPwm1Regs.AQCTLA.bit.ZRO = AQ_SET; // Clear PWM1A on CAD
EPwm1Regs.AQCTLB.bit.CAU = AQ_SET; // Clear PWM1B on CAU
EPwm1Regs.AQCTLB.bit.ZRO = AQ_CLEAR; // Set PWM1B on CAD
//
// Active Low PWMs - Setup Deadband
//
EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
EPwm1Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm1Regs.DBRED = EPWM1_MIN_DB;
EPwm1Regs.DBFED = EPWM1_MIN_DB;
}
void
InitEPwm2Example()
{
EPwm2Regs.ETSEL.bit.SOCAEN = 1; // Enable SOC on A group
EPwm2Regs.ETSEL.bit.SOCASEL = 6; // Select SOC from CMPB on upcount
EPwm2Regs.ETPS.bit.SOCAPRD = 1; // Generate pulse on 1st event
EPwm2Regs.TBPRD = 1499; // Set timer period
EPwm2Regs.TBPHS.half.TBPHS = 500; // Phase is 0
EPwm2Regs.TBCTR = 0x0000; // Clear counter
//
// Setup TBCLK
//
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up
EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Disable phase loading
EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load registers every ZERO
EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
//
// Setup compare
//
EPwm2Regs.CMPA.half.CMPA = duty2*1500;
EPwm2Regs.CMPB=750+EPWM2_MIN_DB;
//
// Set actions
//
EPwm2Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Set PWM1A on CAU
EPwm2Regs.AQCTLA.bit.ZRO = AQ_SET; // Clear PWM1A on CAD
EPwm2Regs.AQCTLB.bit.CAU = AQ_SET; // Clear PWM1B on CAU
EPwm2Regs.AQCTLB.bit.ZRO = AQ_CLEAR; // Set PWM1B on CAD
//
// Active Low PWMs - Setup Deadband
//
EPwm2Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
EPwm2Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm2Regs.DBRED = EPWM2_MIN_DB;
EPwm2Regs.DBFED = EPWM2_MIN_DB;
//EPwm2_DB_Direction = DB_UP;
/*
//
// Interrupt where we will change the Deadband
//
EPwm2Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm2Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm2Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event
*/
}
//
// InitEPwm3Example -
//
void
InitEPwm3Example()
{
EPwm3Regs.ETSEL.bit.SOCAEN = 1; // Enable SOC on A group
EPwm3Regs.ETSEL.bit.SOCASEL = 6; // Select SOC from CMPB on upcount
EPwm3Regs.ETPS.bit.SOCAPRD = 1; // Generate pulse on 1st event
EPwm3Regs.TBPRD = 1499; // Set timer period
EPwm3Regs.TBPHS.half.TBPHS = 1000; // Phase is 0
EPwm3Regs.TBCTR = 0x0000; // Clear counter
//
// Setup TBCLK
//
EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up
EPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Disable phase loading
EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm3Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load registers every ZERO
EPwm3Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm3Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
//
// Setup compare
//
EPwm3Regs.CMPA.half.CMPA = duty3*1500;
EPwm3Regs.CMPB=750+EPWM3_MIN_DB;
//
// Set actions
//
EPwm3Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Set PWM1A on CAU
EPwm3Regs.AQCTLA.bit.ZRO = AQ_SET; // Clear PWM1A on CAD
EPwm3Regs.AQCTLB.bit.CAU = AQ_SET; // Clear PWM1B on CAU
EPwm3Regs.AQCTLB.bit.ZRO = AQ_CLEAR; // Set PWM1B on CAD
//
// Active Low PWMs - Setup Deadband
//
EPwm3Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm3Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
EPwm3Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm3Regs.DBRED = EPWM3_MIN_DB;
EPwm3Regs.DBFED = EPWM3_MIN_DB;
/*
//
// Interrupt where we will change the deadband
//
EPwm3Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm3Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm3Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event
*/
}
//
// End of File
//
Very thanks for your answer.
But I still having the same problem, using the codes that you shared with me: my hardware does not read my inputs. When I use the secuential mode, it reads the inputs (The values are shown in the "Expresions" windows, in the expression: AdcResult.ADCRESULTX), but when I use the configuration simultaneous, this expression does not change (I have activated the "Refresh" button). I do not find the reasons. Why can it happen? Very thanks for your time!
Best regards,
Álvaro
I realised that I am not reading the ADC signal in the right moment, and the ADC interuptions are being fired in random times (using a secuential reading). I am going to explain the purpose of this code:
I want to control 3 buck converters, at 60 kHz. Their PWM signals are shifted 120 degrees, but they read different signals, so their duties can be different. So, I have declared 3 interruptions. In each interruption, I read with ADC module 2 different signals, I make several calculations, and then I actualiced the duty cycle values (COMPA and COMPB, the first is used to make work PWM signal, and the second is used to set the ADC reading time. It must be in a half of the duty cycle). The PWM have dead-times.
Making a summary of the issues:
-Each COMPB's PWM should manage the ADC interruptions fire, but It does not work. There are lot of firing (2 or 3 by cycle) when slould be only one (It is shown by GPIO12,18,22). And nobody fires in the right moment. I think that COMPB does not update its value.
-I can not implement the simultaneous sampling ADC mode.
I really appreciate the help. Get and Understand the code is very important for me.
Best regards,
Álvaro
//PICHICA, TIENES QEU ORDENAR EN STRUCTS: VER QEU VARIABLES GLOBALES Y CUALES GLOBALES
//PICHICA, TIENES QUE PONER TODO EN LECTURA SIMULATANEA
//LLEVAR LAS INTERRUPCIONES INT 1 Y 2 A GRUPO 10. USAR UN SOLO GRUPO
//ORDENAR SOCs. PRIMERO LOS DE LA CORRIENTE DE LA BOBINA, LUEGO LOS DE LA REFERENCIA
//Las funciones de tranferencia del modo Boost y Buck son distintas. Por eso dos controladores. Si queremos usar solo 1, el modo buck se hace lento.
//El ancho de banda del convertidor es donde corta con 0 en las ganancias. Revisar para ver que cubre.
//###########################################################################
//
// FILE: Example_2806xAdcSoc.c
//
// TITLE: Buck-Boost Controller
//
// Control de un convertidor bidireccional buck-boost, con una funci�n de
// transferencia XXX.
//###########################################################################
// $TI Release: F2806x Support Library v2.04.00.00 $
// $Release Date: Sun Sep 29 07:33:29 CDT 2019 $
// $Copyright:
// Copyright (C) 2009-2019 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
//
// Included Files
//
#include "DSP28x_Project.h" // Device Headerfile and Examples Include File
//
// Function Prototypes
//
__interrupt void adc_isr1(void);
__interrupt void adc_isr2(void);
__interrupt void adc_isr3(void);
void Adc_Config(void);
void InitEPwm1Example(void);
void InitEPwm2Example(void);
void InitEPwm3Example(void);
//
// Globals
//
Uint16 ConversionCount;
Uint16 Voltage;
Uint16 Voltagereferencia;
Uint32 EPwm1TimerIntCount;
Uint32 EPwm2TimerIntCount;
Uint32 EPwm3TimerIntCount;
#define EPWM1_MIN_DB 0x0064
#define EPWM2_MIN_DB 0x0064
#define EPWM3_MIN_DB 0x0064
unsigned int corrientefase1;
float duty1 = 0.5;
float dutyold1=0;
float dutyoldold1=0;
float il1=0;
float ilold1=0;
float iloldold1=0;
float duty2 = 0.5;
float dutyold2=0;
float dutyoldold2=0;
float il2=0;
float ilold2=0;
float iloldold2=0;
float referencia=2330;
const int Offset=0;
float duty3 = 0.5;
float dutyold3=0;
float dutyoldold3=0;
float il3=0;
float ilold3=0;
float iloldold3=0;
//
// Main
//
void main(void)
{
//
// Step 1. Initialize System Control:
// PLL, WatchDog, enable Peripheral Clocks
// This example function is found in the F2806x_SysCtrl.c file.
//
InitSysCtrl();
//
// Step 2. Initialize GPIO:
//Inicio pines para ver si da tiempo a c�lculos
EALLOW;
GpioCtrlRegs.GPAMUX1.bit.GPIO12=0x0000;
GpioCtrlRegs.GPAPUD.bit.GPIO12=0x0000;
GpioCtrlRegs.GPADIR.bit.GPIO12=0x0001;
GpioCtrlRegs.GPAQSEL1.bit.GPIO12=0x0000;
GpioCtrlRegs.GPAMUX2.bit.GPIO18=0x0000;
GpioCtrlRegs.GPAPUD.bit.GPIO18=0x0000;
GpioCtrlRegs.GPADIR.bit.GPIO18=0x0001;
GpioCtrlRegs.GPAQSEL2.bit.GPIO18=0x0000;
GpioCtrlRegs.GPAMUX2.bit.GPIO22=0x0000;
GpioCtrlRegs.GPAPUD.bit.GPIO22=0x0000;
GpioCtrlRegs.GPADIR.bit.GPIO22=0x0001;
GpioCtrlRegs.GPAQSEL2.bit.GPIO22=0x0000;
EDIS;
InitEPwm1Gpio();
InitEPwm2Gpio();
InitEPwm3Gpio();
//
// Step 3. Clear all interrupts and initialize PIE vector table:
// Disable CPU interrupts
//
DINT;
//
// Initialize the PIE control registers to their default state.
// The default state is all PIE interrupts disabled and flags
// are cleared.
// This function is found in the F2806x_PieCtrl.c file.
//
InitPieCtrl();
//
// Disable CPU interrupts and clear all CPU interrupt flags:
//
IER = 0x0000;
IFR = 0x0000;
//
// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
// This will populate the entire table, even if the interrupt
// is not used in this example. This is useful for debug purposes.
// The shell ISR routines are found in F2806x_DefaultIsr.c.
// This function is found in F2806x_PieVect.c.
//
InitPieVectTable();
//
// Interrupts that are used in this example are re-mapped to
// ISR functions found within this file.
//
EALLOW; // This is needed to write to EALLOW protected register
PieVectTable.ADCINT1 = &adc_isr1;
EDIS; // This is needed to disable write to EALLOW protected registers
EALLOW; // This is needed to write to EALLOW protected register
PieVectTable.ADCINT2 = &adc_isr2;
EDIS;
EALLOW; // This is needed to write to EALLOW protected register
PieVectTable.ADCINT3 = &adc_isr3;
EDIS;
//
// Step 4. Initialize all the Device Peripherals:
// This function is found in F2806x_InitPeripherals.c
// InitPeripherals(); // Not required for this example
//
InitAdc(); // For this example, init the ADC
AdcOffsetSelfCal();
//
// Step 5. User specific code, enable interrupts:
//
//
// Enable ADCINT1 in PIE
//
PieCtrlRegs.PIEIER1.bit.INTx1 = 1; // Enable INT 1.1 in the PIE
PieCtrlRegs.PIEIER1.bit.INTx2 = 1; // Enable INT 1.2 in the PIE
PieCtrlRegs.PIEIER10.bit.INTx3 = 1; // Enable INT 10.3 in the PIE
IER |= M_INT10; // Enable CPU Interrupt 1
IER |= M_INT1;
EINT; // Enable Global interrupt INTM
ERTM; // Enable Global realtime interrupt DBGM
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;
EDIS;
InitEPwm1Example();
InitEPwm2Example();
InitEPwm3Example();
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;
EDIS;
//
// Configure ADC
//
EALLOW;
AdcRegs.ADCCTL2.bit.ADCNONOVERLAP = 1; // Enable non-overlap mode
//
// ADCINT1 trips after AdcResults latch
//
AdcRegs.ADCCTL1.bit.INTPULSEPOS = 1;
AdcRegs.INTSEL1N2.bit.INT1E = 1; // Enabled ADCINT1
AdcRegs.INTSEL1N2.bit.INT1CONT = 0; // Disable ADCINT1 Continuous mode
AdcRegs.INTSEL1N2.bit.INT2E = 1; // Enabled ADCINT2
AdcRegs.INTSEL1N2.bit.INT2CONT = 0; // Disable ADCINT2 Continuous mode
AdcRegs.INTSEL3N4.bit.INT3E = 1; // Enabled ADCINT3
AdcRegs.INTSEL3N4.bit.INT3CONT = 0; // Disable ADCINT3 Continuous mode
//
// setup EOC1 to trigger ADCINT1 to fire
//
//SEQUENTIAL MODE
AdcRegs.INTSEL1N2.bit.INT1SEL = 1;
AdcRegs.INTSEL1N2.bit.INT2SEL = 1;
AdcRegs.INTSEL3N4.bit.INT3SEL = 1;
/*
//SIMULTANEOUS MODE
AdcRegs.ADCSAMPLEMODE.bit.SIMULEN0=1;
AdcRegs.ADCSOC0CTL.bit.CHSEL = 0;
AdcRegs.ADCSAMPLEMODE.bit.SIMULEN2=1;
AdcRegs.ADCSOC2CTL.bit.CHSEL = 1;
AdcRegs.ADCSAMPLEMODE.bit.SIMULEN4=1;
AdcRegs.ADCSOC4CTL.bit.CHSEL = 2;
//SIMULTANEOUS MODE
//Recomendaci�n del colega de TI. Ojo que al usar SIMULEN, el SOC1 corresponde con EOC1 y as�.
AdcRegs.INTSEL1N2.bit.INT1SEL = 1; // EOC1 triggers INT1
AdcRegs.INTSEL1N2.bit.INT2SEL = 3; // EOC3 triggers INT2
AdcRegs.INTSEL3N4.bit.INT3SEL = 5; // EOC5 triggers INT3
*/
//Sequential mode
AdcRegs.ADCSOC0CTL.bit.CHSEL = 0; // set SOC0 channel select to ADCINA0
AdcRegs.ADCSOC1CTL.bit.CHSEL = 8; // set SOC1 channel select to ADCINB0
AdcRegs.ADCSOC2CTL.bit.CHSEL = 1; // set SOC2 channel select to ADCINA1
AdcRegs.ADCSOC3CTL.bit.CHSEL = 9; // set SOC3 channel select to ADCINB1
AdcRegs.ADCSOC4CTL.bit.CHSEL = 2; // set SOC4 channel select to ADCINA2
AdcRegs.ADCSOC5CTL.bit.CHSEL = 0x000A; // set SOC5 channel select to ADCINB2
/*
// SIMULTANEOUS
AdcRegs.ADCSOC0CTL.bit.TRIGSEL = 5;
AdcRegs.ADCSOC1CTL.bit.TRIGSEL = 0; //make sure that the odd SOCs are disabled.
AdcRegs.ADCSOC2CTL.bit.TRIGSEL = 7;
AdcRegs.ADCSOC3CTL.bit.TRIGSEL = 0;
AdcRegs.ADCSOC4CTL.bit.TRIGSEL = 9;
AdcRegs.ADCSOC5CTL.bit.TRIGSEL = 0;
*/
//
//SEQUENTIAL
// set SOC0 start trigger on EPWM1A, due to round-robin SOC0 converts
// first then SOC1
//
AdcRegs.ADCSOC0CTL.bit.TRIGSEL = 5;
//
// set SOC1 start trigger on EPWM1A, due to round-robin SOC0 converts
// first then SOC1
//
AdcRegs.ADCSOC1CTL.bit.TRIGSEL = 5;
//
// set SOC2 start trigger on EPWM2A, due to round-robin SOC0 converts
// first then SOC1
//
AdcRegs.ADCSOC2CTL.bit.TRIGSEL = 7;
//
// set SOC3 start trigger on EPWM1A, due to round-robin SOC0 converts
// first then SOC1
//
AdcRegs.ADCSOC3CTL.bit.TRIGSEL = 7;
//
// set SOC4 start trigger on EPWM3A, due to round-robin SOC0 converts
// first then SOC1
//
AdcRegs.ADCSOC4CTL.bit.TRIGSEL = 9;
//
// set SOC5 start trigger on EPWM3A, due to round-robin SOC0 converts
// first then SOC1
//
AdcRegs.ADCSOC5CTL.bit.TRIGSEL = 9;
//
// set SOC0 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
//
AdcRegs.ADCSOC0CTL.bit.ACQPS = 6;
//
// set SOC1 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
//
AdcRegs.ADCSOC1CTL.bit.ACQPS = 6;
//
// set SOC0 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
//
AdcRegs.ADCSOC2CTL.bit.ACQPS = 6;
//
// set SOC1 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
//
AdcRegs.ADCSOC3CTL.bit.ACQPS = 6;
//
// set SOC0 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
//
AdcRegs.ADCSOC4CTL.bit.ACQPS = 6;
//
// set SOC1 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
//
AdcRegs.ADCSOC5CTL.bit.ACQPS = 6;
/*
// SIMULTANEOUS
AdcRegs.ADCSOC0CTL.bit.ACQPS = 0x0028;
AdcRegs.ADCSOC2CTL.bit.ACQPS = 0x0028;
AdcRegs.ADCSOC4CTL.bit.ACQPS = 0x0028;
EDIS;
*/
for(;;)
{
}
}
//
// adc_isr -
//
__interrupt void
adc_isr1(void)
{
GpioDataRegs.GPASET.bit.GPIO18=0x0001;
iloldold1=ilold1;
ilold1=il1;
corrientefase1=AdcResult.ADCRESULT0;
il1 = (referencia-(AdcResult.ADCRESULT0-Offset))*0.00081;
//il1 = (AdcResult.ADCRESULT1-(AdcResult.ADCRESULT0-Offset))*0.00081; //Ojo que hay que a�adirle el offset a la entrada
dutyoldold1=dutyold1;
dutyold1=duty1;
duty1 = 0.0007876*il1+0.0001147*ilold1-0.0006729*iloldold1+0.1743*dutyold1+0.8257*dutyoldold1;
//duty1=0.0007876*il1+duty1;
if (duty1 < 0.1)
{
duty1 = 0.1;
}
if (duty1 > 0.9)
{
duty1 = 0.9;
}
EPwm1Regs.CMPA.half.CMPA = (Uint16)(duty1*1500);
EPwm1Regs.CMPB=(Uint16)(duty1*750+EPWM1_MIN_DB);
//
// Clear ADCINT1 flag reinitialize for next SOC
//
AdcRegs.ADCINTFLGCLR.bit.ADCINT1 = 1;
PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; // Acknowledge interrupt to PIE
GpioDataRegs.GPACLEAR.bit.GPIO18=0x0001;
return;
}
__interrupt void
adc_isr2(void)
{
GpioDataRegs.GPASET.bit.GPIO22=0x0001;
iloldold2=ilold2;
ilold2=il2;
//il2 = (referencia-(AdcResult.ADCRESULT3-Offset))*0.00081;
il2 = (AdcResult.ADCRESULT2-(AdcResult.ADCRESULT3-Offset))*0.00081;
dutyoldold2=dutyold2;
dutyold2=duty2;
duty2 = 0.0007876*il2+0.0001147*ilold2-0.0006729*iloldold2+0.1743*dutyold2+0.8257*dutyoldold2;
//duty=0.0007876*il+duty;
if (duty2 < 0.1)
{
duty2 = 0.1;
}
if (duty2 > 0.9)
{
duty2 = 0.9;
}
EPwm2Regs.CMPA.half.CMPA = (Uint16)(duty2*1500);
EPwm2Regs.CMPB=(Uint16)(duty2*750+EPWM2_MIN_DB);
//
// Clear ADCINT1 flag reinitialize for next SOC
//
AdcRegs.ADCINTFLGCLR.bit.ADCINT2 = 1;
PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; // Acknowledge interrupt to PIE
GpioDataRegs.GPACLEAR.bit.GPIO22=0x0001;
return;
}
__interrupt void
adc_isr3(void)
{
GpioDataRegs.GPASET.bit.GPIO12=0x0001;
iloldold3=ilold3;
ilold3=il3;
//il3 = (referencia-(AdcResult.ADCRESULT5-Offset))*0.00081;
il3 = (AdcResult.ADCRESULT4-(AdcResult.ADCRESULT5-Offset))*0.00081; //Ojo que hay que a�adirle el offset a la entrada
dutyoldold3=dutyold3;
dutyold3=duty3;
duty3 = 0.0007876*il3+0.0001147*ilold3-0.0006729*iloldold3+0.1743*dutyold3+0.8257*dutyoldold3;
//dut31=0.0007876*il3+duty3;
if (duty3 < 0.1)
{
duty3 = 0.1;
}
if (duty3 > 0.9)
{
duty3 = 0.9;
}
EPwm3Regs.CMPA.half.CMPA = (Uint16)(duty3*1500);
EPwm3Regs.CMPB=(Uint16)(duty3*750+EPWM3_MIN_DB);
//
// Clear ADCINT3 flag reinitialize for next SOC
//
AdcRegs.ADCINTFLGCLR.bit.ADCINT3 = 1;
PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; // Acknowledge interrupt to PIE grupo 10
GpioDataRegs.GPACLEAR.bit.GPIO12=0x0001;
return;
}
void
InitEPwm1Example()
{
//EN este caso, la salida 40 da 3.3 si duty es 0 y 0 si duty es 1
EPwm1Regs.ETSEL.bit.SOCAEN = 1; // Enable SOC on A group
EPwm1Regs.ETSEL.bit.SOCASEL = 6; // Select SOC from CMPB on upcount
EPwm1Regs.ETPS.bit.SOCAPRD = 1; // Generate pulse on 1st event
EPwm1Regs.TBPRD = 1499; // Set timer period
EPwm1Regs.TBPHS.half.TBPHS = 0x0000; // Phase is a 0
EPwm1Regs.TBCTR = 0x0000; // Clear counter
//
// Setup TBCLK
//
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load registers every ZERO
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
//
// Setup compare
//
EPwm1Regs.CMPA.half.CMPA = duty1*1500;
EPwm1Regs.CMPB=750+EPWM1_MIN_DB;
//
// Set actions
//
EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Set PWM1A on CAU
EPwm1Regs.AQCTLA.bit.ZRO = AQ_SET; // Clear PWM1A on CAD
EPwm1Regs.AQCTLB.bit.CAU = AQ_SET; // Clear PWM1B on CAU
EPwm1Regs.AQCTLB.bit.ZRO = AQ_CLEAR; // Set PWM1B on CAD
//
// Active Low PWMs - Setup Deadband
//
EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
EPwm1Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm1Regs.DBRED = EPWM1_MIN_DB;
EPwm1Regs.DBFED = EPWM1_MIN_DB;
}
void
InitEPwm2Example()
{
EPwm2Regs.ETSEL.bit.SOCAEN = 1; // Enable SOC on A group
EPwm2Regs.ETSEL.bit.SOCASEL = 6; // Select SOC from CMPB on upcount
EPwm2Regs.ETPS.bit.SOCAPRD = 1; // Generate pulse on 1st event
EPwm2Regs.TBPRD = 1499; // Set timer period
EPwm2Regs.TBPHS.half.TBPHS = 500; // Phase is 0
EPwm2Regs.TBCTR = 0x0000; // Clear counter
//
// Setup TBCLK
//
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up
EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Disable phase loading
EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load registers every ZERO
EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
//
// Setup compare
//
EPwm2Regs.CMPA.half.CMPA = duty2*1500;
EPwm2Regs.CMPB=750+EPWM2_MIN_DB;
//
// Set actions
//
EPwm2Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Set PWM1A on CAU
EPwm2Regs.AQCTLA.bit.ZRO = AQ_SET; // Clear PWM1A on CAD
EPwm2Regs.AQCTLB.bit.CAU = AQ_SET; // Clear PWM1B on CAU
EPwm2Regs.AQCTLB.bit.ZRO = AQ_CLEAR; // Set PWM1B on CAD
//
// Active Low PWMs - Setup Deadband
//
EPwm2Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
EPwm2Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm2Regs.DBRED = EPWM2_MIN_DB;
EPwm2Regs.DBFED = EPWM2_MIN_DB;
//EPwm2_DB_Direction = DB_UP;
/*
//
// Interrupt where we will change the Deadband
//
EPwm2Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm2Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm2Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event
*/
}
//
// InitEPwm3Example -
//
void
InitEPwm3Example()
{
EPwm3Regs.ETSEL.bit.SOCAEN = 1; // Enable SOC on A group
EPwm3Regs.ETSEL.bit.SOCASEL = 6; // Select SOC from CMPB on upcount
EPwm3Regs.ETPS.bit.SOCAPRD = 1; // Generate pulse on 1st event
EPwm3Regs.TBPRD = 1499; // Set timer period
EPwm3Regs.TBPHS.half.TBPHS = 1000; // Phase is 0
EPwm3Regs.TBCTR = 0x0000; // Clear counter
//
// Setup TBCLK
//
EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up
EPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Disable phase loading
EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm3Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load registers every ZERO
EPwm3Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm3Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
//
// Setup compare
//
EPwm3Regs.CMPA.half.CMPA = duty3*1500;
EPwm3Regs.CMPB=750+EPWM3_MIN_DB;
//
// Set actions
//
EPwm3Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Set PWM1A on CAU
EPwm3Regs.AQCTLA.bit.ZRO = AQ_SET; // Clear PWM1A on CAD
EPwm3Regs.AQCTLB.bit.CAU = AQ_SET; // Clear PWM1B on CAU
EPwm3Regs.AQCTLB.bit.ZRO = AQ_CLEAR; // Set PWM1B on CAD
//
// Active Low PWMs - Setup Deadband
//
EPwm3Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm3Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
EPwm3Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm3Regs.DBRED = EPWM3_MIN_DB;
EPwm3Regs.DBFED = EPWM3_MIN_DB;
/*
//
// Interrupt where we will change the deadband
//
EPwm3Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm3Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm3Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event
*/
}
//
// End of File
//
Alvaro,
I need to look at the code in more detail; but one thing I'd like to try enable continous run for the ADCINTs
At line 235
AdcRegs.ADCCTL1.bit.INTPULSEPOS = 1;
AdcRegs.INTSEL1N2.bit.INT1E = 1; // Enabled ADCINT1
AdcRegs.INTSEL1N2.bit.INT1CONT = 1; // Enable ADCINT1 Continuous mode
AdcRegs.INTSEL1N2.bit.INT2E = 1; // Enabled ADCINT2
AdcRegs.INTSEL1N2.bit.INT2CONT = 1; // Enable ADCINT2 Continuous mode
AdcRegs.INTSEL3N4.bit.INT3E = 1; // Enabled ADCINT3
AdcRegs.INTSEL3N4.bit.INT3CONT = 1; // Enable ADCINT3 Continuous mode
Best,
Matthew
I found the problem and now, I think everything is working: The problem was in the function:" AdcOffsetSelfCal(); ". This function, which was created by TI team, adjust the ADC offset. I do not exactly how it works but, it modifies " ADCINTSOCSEL1 and ADCINTSOCSEL2 and it never return to the initial configuration. I set this configuration and now, the simultaneus sampling works.
Very thanks for your help. I cannot solve this mess without you.
Best regards,
Álvaro