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TMS320F280049: SDFM timing requirement.

Luke Chen
Expert 5090 points
Part Number: TMS320F280049


Hi all,

In F28004x datasheet, we say that when using ASYNC GPIO option, the minimum setup time and hold time are 5ns, this 5ns is needed to pass signal from GPIO to SDFM, right?  When using SYNC GPIO option, the minimum setup time and hold time will be 2 * SYSCLK period, I have one question about this timing requirement below,

When SYNC option, because SYSCLK is not synchronous to the clock/data signals from modulator IC, it could be timing difference between signals and SYSCLK when GPIO module get correct data and the worst case could be up to 1 * SYSCLK period(I think this period should refer to GPIO Qualification Sampling Period).

So in my opinion, when using SYNC GPIO option, the minimum setup/hold time should be 1 * SYSCLK period + 5ns, where period refer to GPIO Qualification Sampling Period and 5ns is the minimum timing requirement as ASYNC option does.

Please advise your comments with my idea above, thanks for help.

Regards,

Luke

  • 0
    TI__Guru 55700 points

    Luke,

    The setup and hold time provided in F280049 datasheet is indeed correct. The values found in your datasheet is based on timing closure results and guaranteed by design

    Regards,

    Manoj

  • 0 in reply to Manoj Santha Mohan
    TI__Expert 5090 points

    Manoj,

    We need setup time of data line, because we hope that data line should be ready before clock line goes high level generating rising edge and capture data.

    When using SYNC GPIO option, it should be related to GPIO qualification sampling period control setting, although the default sampling period is PLLSYSCLK after device reset.

    Let's think of one condition of SYNC option, if users set GPIO qualification sampling period QUALPRDx = PLLSYSCLK/16, is the minimum setup time still 2 * SYSCLK period? Is it reasonable?

    Because data and clock are not synchronous to PLLSYSCLK/16, SYNC option maybe get high level data and clock at the same time with 2 * SYSCLK setup time, and then pass these signals to SDFM. SDFM even cannot get correct bit data, am I thinking wrong?

    Regards,

    Luke

  • 0 in reply to Luke Chen
    TI__Guru 55700 points

    Luke,

    GPIO_SYNC option just synchronizes the SDCLK and SDDATA bit streams with respect SYSCLK. GPIO_SYNC option doesn't qualify the GPIO signals.

    Therefore settings provided in QUALPRDx doesn't affect GPIO when GPIO_QUAL = GPIO_SYNC. QUALPRDx settings take into effect only when GPIO_QUAL = 3-sample (or) 6-sample window.

    Regards,

    Manoj

  • 0 in reply to Manoj Santha Mohan
    TI__Expert 5090 points

    Manoj,

    Yes, you are right. I misunderstand this.

    The signals of SYNC and QUAL(3/6 samples) are first synchronized to the system clock(SYSCLKOUT) first.

    Thanks for your response,

    Luke

  • 0 in reply to Luke Chen
    TI__Expert 5090 points

    Manoj,

    I don't create another thread and I have more items need your comments.

    One of my customer uses F28377D GPIO16-21(SD1 CH1-CH3) for motor control current sensing, according to Electrical Characteristics table of datasheet below, SDFM will capture data when the voltage level of SDCLK is above 2.0V(low to high and generate rising edge), is it correct?

    This customer use AMC1305 as SD modulator IC, we know that AMC1305 guarantees to output data within 15ns when receiving a SDCLK falling edge. F28377D is executed at 200MHz SYSCLK and set SDFM as GPIO SYNC option, So 15ns + 2 * SYSCLK periods equals 25ns, and this 25ns is exactly half clock cycle when the frequency of SDCLK is 20MHz.

    Customer usually will add RC filters on SDCLK and SDDATA to improve system noise immunity, RC filters will reduce the slope of signals and resulting in insufficient SDDATA setup time, maybe 9.8ns or 9.6ns of setup time for example.

    According to our datasheet, the minimum setup time needed is 10ns(SYSCLK = 200MHz). How should I respond this situation? Should I say we won't guarantee SDFM is able to get correct data since the setup time doesn't meet the minimum requirement in datasheet?

    In real use case, because AMC devices just guarantee to output data WITHIN 15ns, it is difficult to have 10ns SDDATA setup time actually. And, GPIO ASYNC option seems not robust enough of this application. Do you have any further suggestion of this situation please?

    Please advise your idea, your help is appreciated.

    Regards,

    Luke

  • 0 in reply to Luke Chen
    TI__Guru 55700 points

    Luke,

    1) Yes, SDFM will capture a 'HIGH' signal if the voltage level of SDCLK is greater than 2v and will capture 'LOW' signal if the voltage level of SDCLK is less than   0.8V.

    2) Any time SDFM timing requirements aren't met, TI CANNOT guarantee proper operation of SDFM. Either customer has to choose RC filter which wouldn't reduce the setup / hold time < 10ns. If not, they have to rely on GPIO_SYNC feature to provide better noise immunity.

    Regards,

    Manoj