Part Number: TMS320F28374S
Other Parts Discussed in Thread: CONTROLSUITE, C2000WARE
I am in need of some clarification regarding CAN_REGS for CAN bit timing. Specifically bit timing register CAN_BTR, field TSEG1 (bits 11-8). I am reading the TMS320F2837xS Delfino Microcontrollers Technical Reference Manual, revised on September 2017.The register field description in table 21-13 on pg 2268 says its the time segment before the sample point and the actual Tseg1 is the programmed register value + 1. The wording "time segment before the sample point" seems to suggest that this time includes Synchronization Segment (Sync_Seg), Propagation Time Segment (Prop_seg), and Phase Buffer Segment 1 (Phase_Seg1/SJW). However section 21.12.2 on pg 2250 says "Therefore the length of the Bit time is (programmed values) [TSEG1 + TSEG2 + 3]tq or (functional values)[Sync_Seg + Prop_Seg + Phase_Seg1 + Phase_Seg2]tq. From table 21-13 on pg 2268 it states that actual Tseg2 is programmed TSEG2 register value + 1. From table 21-4 on pg 2245 it states that Syc_Seg is fixed at 1 tq. Therefore I assume that the "+3" in the statement "length of the Bit time is (programmed values) [TSEG1 + TSEG2 + 3]tq" comes from the fact that actual Tseg1 is programmed TSEG1 register value + 1, actual Tseg2 is programmed TSEG2 register value + 1, and the third + 1 comes from Sync_seg being fixed at 1 tq. However that would mean that actual Tseg1 does not include Sync_seg, which contradicts my interpretation of the register field description in table 21-13 pg 2268.
When I look at the example C header in C:\ti\controlSUITE\device_support\F2837xS\v210\F2837xS_common\driverlib\can.h there is a typedef struct called tCANBitClkParams that has a member called uSyncPropPhase1Seg. The comments in the code says this field holds the sum of the Sync_Seg, Prop_Seg, and Phase_Seg1. This struct tCANBitClkParams is used to set CAN bit timing using function CANBitTimingSet. When looking at the example C source file in C:\ti\controlSUITE\device_support\F2837xS\v210\F2837xS_common\driverlib\can.c, in the CANBitTimingSet function definition on line 673, it states
uBitReg |= ((pClkParms->uSyncPropPhase1Seg - 1) << 8) & CAN_BTR_TSEG1_M;
That line of code sets the TSEG1 register field to (uSyncPropPhase1Seg - 1). The minus one is because uSyncPropPhase1Seg is the actual value and actual value is programmed register value + 1. That would mean that actual Tseg1 does include Sync_Seg. However that would contradict my interpretation of the length of the Bit time described in section 21.12.2 pg 2250 of the technical reference manual.
Also Section 21.12.2 pg 2249 of the technical reference manual states that "Sum of Prop_Seg and Phase_Seg1 (as TSEG1) ...". I interpret that statement to mean that TSEG1 does not include Sync_Seg.
So you can see that there are many discrepancies that make it difficult to understand whether or not actual Tseg1 includes Sync_Seg or not. My exact question is: does CAN_REGS, bit timing register CAN_BTR, field TSEG1 (bits 11-8) programmed = ( (actual)[Sync_Seg + Prop_Seg + Phase_Seg1] ) - 1, or does TSEG1 programmed = ( (actual)[Prop_Seg + Phase_Seg1] ) - 1?
