• State TI Thinks Resolved
  • Locked Locked
  • Replies 3 replies
  • Answers 1 answer
  • Subscribers 82 subscribers
  • Views 353 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TIDM-1000: Control loop

Alberto Est
Prodigy 50 points
Part Number: TIDM-1000
Other Parts Discussed in Thread: SFRA,

Hi everyone,

I am trying to build my custom Vienna converter and now I am stucked in how to make the control loop work in a good way. I have some questions:

1. How I have to select the correct values in Compensation Designer to make a good regulation of current and voltage loop? I followed the guide but I could not understand how to select this values.

2. Moreover, I have some problems of bus unbalance trips, how i should set the sequence of things to do to achieve a solution of this problem?

Looking forward to hearing from you.

Kind regards,

Alberto E.

  • 0
    TI__Genius 15935 points

    Hi Alberto,

    1. You can import the data measured by SFRA into compensation designer and tune the current and voltage loop accordingly. The coefficient value is selected based on the bandwidth, phase margin and gain margin. 

    The user guide should give you more information 

    2. In our reference design, we have a voltage balanced loop which is enabled in build 4. And the TIDM-1000 user guide has the voltage balanced loop related information.

    Thanks.

    Regards,

    Chen

  • 0 in reply to Chen Jiang ti
    Prodigy 50 points

    Hello Chen,

    Thank you very much for your answer

    "The coefficient value is selected based on the bandwidth, phase margin and gain margin." The problem is that I don't know how to do this, if you could help me in order to select this coefficients and get a good tune I would be very greatful.

    In 2nd question I meant that I get bus unbalance trip even in build 4, and of course following the user guide. I think the problem of this is the regulation and the coefficients, but maybe I am missing something.

    Kind regards,

    Alberto E

  • 0 in reply to Alberto Est
    TI__Genius 15935 points

    Alberto,

    1. I will firstly suggest you to take a look at two videos below.
    https://www.youtube.com/watch?v=PRPysUlMxa8

    https://www.youtube.com/watch?v=8z8PpZdYh7U

    These can give you a rough idea how SFRA and compensation designer works. 

    If you still have trouble tuning the loop, please attach the SFRA pic(by running SFRA) so I can take l look at it.

    2. Could you please give me more information of your test? Is everything ok with current and voltage loop closed(no voltage balanced loop)? At what point does the trip happen? 

    I will suggest to get the SFRA results for each build and see if the issue is only related to the voltage balanced loop. 

    Regards,

    Chen