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TMS320F28069: Correct SOC window for ADC to get consistent results..

venkatesh chilapur
Mastermind 6460 points

Part Number: TMS320F28069

Hi all,

I’ve read the ADC input block for F280xx and all is clear, particularly regarding SOC window and the related TI documentation that I’ve read too.

 But I want to know what are best practices? I know this is very much dependant on the circuitry for voltage sampling that feeds the ADC.

In my case I have two sensors I’m looking at: Voltage after DCDC and Current after DCDC (Vout and Iout).

The DCDC works with a 100kHz, so I thought to use the same PWM to trigger the ADC.

 

If I change my SOC size, I noticed following output in from the ADC block (in uint16):

 

SOC window

Vout ADC

Iout ADC

7

~1681

~235

64

~1682

~284

 

The load current is kept the same. I see that Iout changes quite much between SOC size 7 or 64.

 

So what is the guidance:

  1. For Vout: is the same with SOC 7 or 64. What should I choose ? Is 64 slightly more precise/filtered? Is 7 much faster on the computational side? Should I always go for the small one if I want performance? Can you gauge the impact?

 

  1. For Iout: is probably the circuitry that is too slow to load up the corresponding voltage for the ADC. I’ve tried to switch to 20 kHz, but had similar results (SOC7: 305, SOC64:340). Should I again slow down the trigger until I reach a “steady state”eg I always get the same number independent from window size?
  • 0
    TI__Guru* 85850 points

    Venkatesh,

    Your point on #1 is correct; a smaller SOC size will give a faster overall conversion at the expense of a smaller amount of time to charge the S/H capacitor inside the ADC.  A larger value should allow more time for the S/H cap to charge/acheive steady state with the external signal; but will slow down the overall sample rate of the converter.

    Can you comment on any difference in the input circuit on the Vout signal vs the Iout signal?  From your data it would appear that the Vout signal is more well driven or have a lower input impedance than the Iout signal.

    Your point on changing the S/H window time until you hit steady state can also be applied; also note that you can have a different sample and hold value for each channel; so you could leave the Vout value alone(small) and just modulate the Iout to get a stable value.

    An alternative to modulating the sample and hold to find the sweet spot, would be to double or triple sample the Iout(using the same trigger to pend multiple SOCs) with the min S/H time and see if it resolves to steady state after a certain time, and then back calculate the needed S/H time.

    Finally, I want to point out there is an errata regarding the first sample from an ADC idle state; there will be much higher amount of error on this first sample from idle; just want to make sure that we are not also seeing this effect for either Vout or Iout.

    Look forward to your comments on the above.

    Best,
    Matthew