TMS320F28374S: About EMIF write cycle time

Hi U-SK,

Due to the holidays, please expect a reply by December 31st.

Best Regards,

Marlyn

Hi,

You may be able to use the following applications note to help resolve your question (including the register configuration tool mentioned in its appendix):
https://www.ti.com/lit/sprac96


Thank you,
Brett

Hi,

Yes, your calculation is correct.

Regards,

Vivek Singh

Hi Vivek,

Thank you for your answer.

I have additional question.

 The waveform measured at the time of register setting posted the other day is as follows.

Are there any probable cause that the write cycle time is shorter than the calculation time?

My register setting is as follows:

The reason for EW = 1 is that the wait signal may be sent from the connection target in the actual development product. When measured, the Wait signal was always High and not asserted.(So I think EWC = 0 at the formula when EW=1)

Clock setting is following:

According to above setting, The clock certainly seems to be set at 99MHz.

I am wondering because the waveform is different from the calculation.

Could you give me any advises?

Regards,

U-SK

U-SK,

It may be a good exercise to observe the XCLKOUT signal to confirm the SYSCLK frequency. It should also be possible to observe the EM1CLK signal to confirm the EMIF frequency.

-Tommy

Additional 2 cycle (+2 component)  is for internal delay which you'll not see in the waveform.

Regards,

Vivek Singh

Hi Tommy,

Thank you for your reply.

I will also check the XCLKOUT waveform if necessary.

Regards,

U-SK

Hi Vivek,

Thank you for your reply.

EMIF write cycle time seems to be No.15 in the below figure in the datasheet.

Therefore, I thought that the EMIF write cycle time meant the time between when the EMxCS signal(waveform) went low and when it went high.

What concretely is "internal delay"?

>Additional 2 cycle (+2 component)  is for internal delay which you'll not see in the waveform.

Where is above statement described in TI documents?

Regards,

U-SK