Tool/software: TI C/C++ Compiler
Hi Manoj,
I did the configuration of DMA channel like this:
#pragma DATA_SECTION(RsvExc_DutyCycle_PreCfg_Table, "ramgs2");
uint16_t RsvExc_DutyCycle_PreCfg_Table[RESEXC_SAMPLE_DEPTH] = {
0x0050,
0x0064,
0x0078,
0x008C,
0x00A0,
0x00B4,
0x00C8,
0x00DC,
0x00F0,
0x0104,
0x0118,
0x012C,
0x0140,
0x0154,
0x0168,
0x017C,
0x0190,
0x01A4,
0x01B8,
0x01CC,
};
const Dma_ChannelConfigType DmaChn_RsvExcDutyCycle_t={
DMA_CH1_BASE, //Dma_Base;
(const void*) (EPWM11_BASE + EPWM_O_CMPB+1), //Dma_DestAddr;
&RsvExc_DutyCycle_PreCfg_Table[0], //Dma_SrcAddr;
1, //Dma_BurstSize;
1, //Dma_BurstSrcStep;
0, //Dma_BurstDestStep;
RESEXC_SAMPLE_DEPTH, //Dma_TransferSize;
1, //Dma_TransferSrcStep;
0, //Dma_TransferDestStep;
RESEXC_SAMPLE_DEPTH, //Dma_SrcWrapSize;
0, //Dma_WrapSrcStep;
RESEXC_SAMPLE_DEPTH, //Dma_DestWrapSize;
0, //Dma_WrapDestStep;
DMA_TRIGGER_EPWM11SOCA, //Dma_TrigSrc;
DMA_CFG_ONESHOT_DISABLE |
DMA_CFG_CONTINUOUS_ENABLE |
DMA_CFG_SIZE_16BIT, //Dma_Mode;
};
void Dma_Init(Dma_ChannelConfigType dmaChn)
{
DMA_initController();
DMA_configAddresses(dmaChn.Dma_Base, dmaChn.Dma_DestAddr, dmaChn.Dma_SrcAddr);
DMA_configBurst(dmaChn.Dma_Base, dmaChn.Dma_BurstSize, dmaChn.Dma_BurstSrcStep, dmaChn.Dma_BurstDestStep);
DMA_configTransfer(dmaChn.Dma_Base, dmaChn.Dma_TransferSize, dmaChn.Dma_TransferSrcStep, dmaChn.Dma_TransferDestStep);
DMA_configWrap(dmaChn.Dma_Base, dmaChn.Dma_SrcWrapSize, dmaChn.Dma_WrapSrcStep, dmaChn.Dma_DestWrapSize, dmaChn.Dma_WrapDestStep);
DMA_configMode(dmaChn.Dma_Base, dmaChn.Dma_TrigSrc, dmaChn.Dma_Mode);
DMA_enableTrigger(dmaChn.Dma_Base);
DMA_startChannel(dmaChn.Dma_Base);
}
Based on the code above, I found several abnormal behaviors of DMA modules.
First, and deserve to be mentioned, I got seemingly correct transfer result from the duty cycle table( i.e. RsvExc_DutyCycle_PreCfg_Table) to compare B register of EPWM11
(i.e. (EPWM11_BASE + EPWM_O_CMPB+1)) based on aforementioned code. But the WRAP configuration is different from your advice. What's more, I still got the
same seemingly correct result while I commented the code statements like this:
//DMA_configWrap(dmaChn.Dma_Base, dmaChn.Dma_SrcWrapSize, dmaChn.Dma_WrapSrcStep, dmaChn.Dma_DestWrapSize, dmaChn.Dma_WrapDestStep);
It seems like that the WRAP feature dosen't work at all. But the DMA transfer could continue when the table reaches its end, and restart from the beginning of the table just like the WRAP feature does. So what's wrong with me? I got confused.
Second, accoding to your advices, I did the configuration of DMA channel with the WRAP source step of negative value of BufferSize of RsvExc_DutyCycle_PreCfg_Table[]:
const Dma_ChannelConfigType DmaChn_RsvExcDutyCycle_t={
DMA_CH1_BASE, //Dma_Base;
(const void*) (EPWM11_BASE + EPWM_O_CMPB+1), //Dma_DestAddr;
&RsvExc_DutyCycle_PreCfg_Table[0], //Dma_SrcAddr;
1, //Dma_BurstSize;
1, //Dma_BurstSrcStep;
0, //Dma_BurstDestStep;
RESEXC_SAMPLE_DEPTH, //Dma_TransferSize;
1, //Dma_TransferSrcStep;
0, //Dma_TransferDestStep;
RESEXC_SAMPLE_DEPTH, //Dma_SrcWrapSize;
-RESEXC_SAMPLE_DEPTH, //Dma_WrapSrcStep;
RESEXC_SAMPLE_DEPTH, //Dma_DestWrapSize;
0, //Dma_WrapDestStep;
DMA_TRIGGER_EPWM11SOCA, //Dma_TrigSrc;
DMA_CFG_ONESHOT_DISABLE |
DMA_CFG_CONTINUOUS_ENABLE |
DMA_CFG_SIZE_16BIT, //Dma_Mode;
};
However, the current address pointer dosen't wrap around to the begaining of the table; on the contrary, it reaches the address of &RsvExc_DutyCycle_PreCfg_Table[0] minus RESEXC_SAMPLE_DEPTH. So I think that I have not understand the WRAP correctly.
Third, I use another DMA channel which also triggered by DMA_TRIGGER_EPWM11SOCA to read time stamp of TBCTR of another EPWM module.
But the time intervals are enlarged oddly. When I use another triggering source like DMA_TRIGGER_EPWM13SOCA which is different from former, the result(time intervals) got right. Isn't it permitted that the configuration of two DMA channels with the same trigger source?
Any unclear points, please tell me. Thanks.
