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TMS320F28388D: SPI Communication Between DSPs

Part Number: TMS320F28388D

Hello all,

From the C200ware library, I get the demo project of SPI communication based on external loop features. And I want to adapt it to SPI communication between DSPs, e.g. one is TMS320F28388D, and another also

TMS320F28388D. However, I have some problems with this. Following are the steps that I've done:

Assumptions are that: one DSP is called DSP_A, and its SPI module is named DSP_A_SPIB; the other DSP is called DSP_B, and its SPI module is named DSP_A_SPIB.

First, DSP_A_SPIB is configured as the SPI master, and DSP_B_SPIB the slave.

Second, both DSP_A_SPIB and DSP_B_SPIB use the same transfer protocol of SPI_PROT_POL0PHA0.

Third, as SPI master, DSP_A_SPIB start the SPI communication by calling the function API of SPI_writeDataNonBlocking; as SPI slave, DSP_B_SPIB prepare transmitting data by calling the function of SPI_writeDataNonBlocking too. The followling code is corresponding to the third step:

        SPI_writeDataNonBlocking(SPIB_BASE, TxData_SPIB[i]);

The duplex communication between DSP_A_SPIB and DSP_B_SPIB is designed like this:

When I disable the data trasnmission of slave DSP (i.e. the right one) by calling the function API of SPI_disableTalk, the data transmitted from DSP_A_SPIB to DSP_B_SPIB is normal. However, when I enable the

data trasnmission of slave DSP, some data frames are lost in the transmission. I don't know what happened and how to cope with it now.

I think that the key point is to prepare data in the TX buffer of salve DSP before the master DSP start the data transmission, but how to synchronize among DSPs?

That's all, pls help me. Thanks a lot!

QL

  • Hi,

    A quick point - Please make sure you are using common ground for both the DSP.

    Whitney will provide further detail on this.

    Regards,

    Vivek Singh

  • Do you have a logic analyzer or scope or some other means of seeing the transmissions on the signals? When you say frames are lost, are you receiving incorrect data for the missing frames or are you actually receiving the wrong number of transmissions?

    Your theory that the master is starting the transmission before the slave side is ready is possible. SPI natively doesn't provide a mechanism for that synchronization--you'll need to come up with a solution in your system to handle it. How often is the master initiating a transmission? How often is the slave writing to the TX buffer? If the timing is too unpredictable, do you have a spare GPIO you can use to signal whether or not the slave side is ready?

    Whitney