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F28M35H52C: EPI SDRAM MAP

Part Number: F28M35H52C

Hi all:

      I have read the datasheet of F28M35H52.This chip has two core(M3+C2000),both can access the EPI bus.

      In DS Page 155, I found that the EPI address map  in C2000 is 0x30 0000-0x3F 7FFF(16bit),and in M3 is 0x6000 0000 - 0xDFFF FFFF(8bit).

      Is that wrong?I think  "0x30 0000-0x3F 7FFF" can not map "1G *  16bit" space.

      And ,how to check the data in external sdram in CCS. I change the GEL file,it works well in M3 project but dosen't work in C2000 project. 

                                                                                                                                                                                                       Thanks.

  • anvaya said:
          In DS Page 155, I found that the EPI address map  in C2000 is 0x30 0000-0x3F 7FFF(16bit),and in M3 is 0x6000 0000 - 0xDFFF FFFF(8bit).

          Is that wrong?I think  "0x30 0000-0x3F 7FFF" can not map "1G *  16bit" space.

    The 2G value is wrong for the Control Subsystem. It appears to be a copy-paste error taken from the Master Subsystem. The reach for the memory space shown is 2M. So the C28 will have reduced access to external memory when compared to the M3.

    It should be noted however, that even though the memory space reserved for EPI on the Master Subsystem allows for 2G of reach, the usable address range is limited by the number of available EPI address signals. In the case of SDRAM, memory sizes are limited to 64M.

    anvaya said:
          And ,how to check the data in external sdram in CCS. I change the GEL file,it works well in M3 project but dosen't work in C2000 project.

    Once the EPI is configured, external memory should be available to both the C28 and M3. If using a standalone Control project, the C28x will need to configure the EPI registers. If using a mixed project, it will be up to the developer to decide if the EPI should be configured by M3 or C28x.

    How are you checking the SDRAM?

  • Hi tlee:

    Thanks for reply.I will change my design if the reach for c2000 memory space is only 2M.

    I want to check the SDRAM in the memory browser tool.

  • Anvaya,

    You will want to either A) set a breakpoint in the program some time after the EPI has been configured in order to observe the SDRAM contents from the browser tool, or B) use a GEL function to configure the EPI.

    Also note that your selection of the active CPU from the target connection will determine which core is being used to observe the memory.

    -Tommy

  • Anvaya,

    Are you still having trouble?

    -Tommy

  • thanks,no more trouble