Other Parts Discussed in Thread: TMS320F2812
We are connecting a MPC5566 to a TMS320F2812 via a SPI bus.
The MPC5566 is master and the DSP is Slave.
The DSP is configured as "Falling Edge without delay" as described in SPRU059E.
The data is sampled on the rising edge of the SPICLK, and changes on the falling edge of the clock.
The data sheet (SPRS174L, Dec 2004) shows a required hold time of 0.5tc(SPC). (tsu(SPCH-SIMO)
The MPC5566 processor specifies a hold time of -5 ns after the falling edge.
This results in a Hold time voilation if the tc(SPC) is the 303 ns for the bus.
The 0.5 requirement does not allow for clock skewing, or propogation delay differential between clock and data.
Is the tc(SPC) of 20 the 4tc(LCO) or the 606ns of the clock used?
I would expect the real requirement is 2 * tc(LCO), or 120 ns for 2 cycles of the 16.6 MHz LSPCLK. This would be 0.5 * tc(SPC); where tc(SPC) = 4 *tc(LCO).