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After reading the power sequencing requirements on the datasheet that said :
I'm thinking to connect 1.2v regulator (to supply VDD) after 3v3 (VDDIO and VDDA supply) and connect like in these schema.
In these approach I'll be sure that VDD will always be less than VDDIO.
Do you think it's a good idea (apart from power energy efficiency, just in concept)
Thanks!
Pablo Slavkin
Hi Pablo,
Yes, that is a good idea, it should satisfy the VDD requirements.
TI also recommends to validate the timing once the board is ready on the O-Scope to make sure it meets the requirement.
Regards,
Nirav