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TMS320F28379D: Questions about HRPWM limitations

aapor
Prodigy 40 points

Part Number: TMS320F28379D

I have implemented code for high resolution duty cycle and dead band control. I have some questions about the limitations described in the documentation related to HRPWM.

1. The duty cycle limitation (chapter 15.14.1.5.3 in the technical manual) is that when using HRPWM, the minumum duty should be 3 cycles. For smaller values the HRPWM should be disabled. A quote from the manual:
"When high-resolution period control is disabled, regular PWM duty control is fully operational down to 0% duty cycle despite the unavailability of HRPWM features in the first three cycles."

My question is that is it enough to set the high resolution registers to 0 (CMPAHR and CMPBHR) to disable the HRPWM features in this case? Or do I have to re-initialize the module with the HRPWM features completely disabled?

2. My other question is related to the same limitation in the HR dead band feature. In HR dead band documentation (15.14.1.6) there is a note which says:
"Just like the duty cycle restrictions when using HRPWM, the DBRED and DBFED values must be greater than 3 to use hi-res deadband."

However, in chapter 15.14.1.5.3, a bullet point says:
"When using DBREDHR or DBFEDHR, DBRED and/or DBFED (the register corresponding to the edge with hi-resolution displacement) must be greater than or equal to 7."

So, is it 3 or 7, or have I understood something wrong?

I have also done some tests on my own, and it seems like the HR dead band adjustment works for all DBRED/DBFED values. I can adjust the dead band value upwards from 0 nanoseconds in HR steps without any issues. I am sure there is a good reason for the 3 cycle limitation, but in practice I have not been able to find any issues with HR dead band operation below 3 cycles. Can you elaborate what might make the HR dead band have undefined behavior when operating below 3 cycles?

Thank you.

  • 0
    TI__Guru 52220 points

    1. If you set the HR portion of the duty to ZERO, you will be VERY close to having disable HR, but there will be i believe a 2-MEP step delay still present.

    You can just DISABLE the HR module if that is not tolerable in the system.

    2. There may be possible glitches if you dont abide by the minimum value rule.

  • 0 in reply to Nima Eskandari
    Prodigy 40 points

    Thank you for the response.

    1. A 2-MEP step delay is not an issue. I am interested in avoiding the possible undefined behavior that might happen below 3 cycles. Does setting the HR portion to zero do this? I am ok with coarse step size near the duty cycle limits.

    2. Ok. Is the mentioned coarse clock limit for the HR dead band 3 or 7 cycles? Also, as in question 1, I am interested if I can avoid the undefined behavior below the limit by setting the HR portion to zero.

  • 0 in reply to aapor
    TI__Guru 52220 points

    1. As long as your coarse step is out of the 3 cycle range.

    2. The value is 7.

  • 0 in reply to Nima Eskandari
    Prodigy 40 points

    Thank you for the clarification. It is a shame that the minimum value is 7. It corresponds to 35ns of mimimum high resolution dead time which can be high for modern GaN and SiC devices.