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TMS320F28388D: Independence/Interference of CPU Cores

Robert Finger
Genius 17537 points
Part Number: TMS320F28388D


Team,

A customer of mine considers F2838xD for a safety related application. It's important to have both CPU cores independent from each other. There should be no interference and latency should be deterministic.

For shared memories, the documentation is relatively clear as it states the presence of fixed and round robin arbitration.

 For peripherals however, it’s not 100% clear. Is the following understanding of my customer correct?

  1. Peripherals that can be assigned to CPU1 or CPU2 and have common selectable secondary masters
    [Possible interference] I believe that here concurrent access can occur between the CPU1 (or CPU2) and the selected secondary master. However, the CPU which has not been assigned doesn’t have access to these peripherals so no CPU1/CPU2 interference.

  2. Peripherals that can be assigned to CPU1 or CPU2 subsystems
    [Possible interference] Same as #1.

  3. Peripherals and Device Configuration Registers only on CPU1 subsystem
    [Possible interference] Possible concurrent accesses between CPUx, CLAx and DMAx.

  4. Accessible by only one CPU at a time by Semaphore
    [No interference] Only CPU have accesses and only one a time.

  5. Peripherals and Registers with Unique Copies of Registers for each CPU and CLA Master
    [No interference] Each CPU and CLA master sees the registers on its own bus and concurrent access can be performed without interference.


    However, for #1 to #3 with a smart assignment interferences could be avoided (eg. ensuring through SW scheduling that concurrent accesses can’t occur).

If there is anything wrong in this assumptions, please let me know!

Thanks & best regards,
  Robert

  • 0
    TI__Guru** 115431 points

    Hi Robert,

    Peripherals that can be assigned to CPU1 or CPU2 and have common selectable secondary masters
    [Possible interference] I believe that here concurrent access can occur between the CPU1 (or CPU2) and the selected secondary master. However, the CPU which has not been assigned doesn’t have access to these peripherals so no CPU1/CPU2 interference.

    What do you mean by "common selectable secondary masters". Both CPU have their own secondary masters (CLA/DMA) and configuration register to select the same.

    Peripherals that can be assigned to CPU1 or CPU2 subsystems
    [Possible interference] Same as #1.

    Peripheral can only be accessed by CPU which has been assigned the ownership and this assignment can be done by CPU1 only. So there should not be any interference.

    Peripherals and Device Configuration Registers only on CPU1 subsystem
    [Possible interference] Possible concurrent accesses between CPUx, CLAx and DMAx.

    All the configuration registers are accessible from CPU1 only and not by it's CLA or DMA. For peripheral access, either DMA or CLA can have access (not both, based on secondary master select).

    Accessible by only one CPU at a time by Semaphore
    [No interference] Only CPU have accesses and only one a time.

    Not true. In some cases reads are always allowed by other CPU (e.g. EMIF).

    Peripherals and Registers with Unique Copies of Registers for each CPU and CLA Master
    [No interference] Each CPU and CLA master sees the registers on its own bus and concurrent access can be performed without interference.

    That is correct but not many example like that. If you have some specific IP in mind, please let me know.

    However, for #1 to #3 with a smart assignment interferences could be avoided (eg. ensuring through SW scheduling that concurrent accesses can’t occur).

    That is correct.

    Regards,

    Vivek Singh

  • 0 in reply to Vivek Singh
    Expert 2816 points

    Hi,

    Being the source of the question, I will answer to your message.

    Vivek Singh said:

    Peripherals that can be assigned to CPU1 or CPU2 and have common selectable secondary masters
    [Possible interference] I believe that here concurrent access can occur between the CPU1 (or CPU2) and the selected secondary master. However, the CPU which has not been assigned doesn’t have access to these peripherals so no CPU1/CPU2 interference.
    What do you mean by "common selectable secondary masters". Both CPU have their own secondary masters (CLA/DMA) and configuration register to select the same.

    Well this is the terminology you use in the section 6.5 of the datasheet.

    But basically my question was related to the possible interference, so I guess it can occur if both the CPU and its secondary master accesses the peripheral at the same time.

    Vivek Singh said:
    Peripherals that can be assigned to CPU1 or CPU2 subsystems
    [Possible interference] Same as #1.
    Peripheral can only be accessed by CPU which has been assigned the ownership and this assignment can be done by CPU1 only. So there should not be any interference.

    Ok

    Vivek Singh said:
    Peripherals and Device Configuration Registers only on CPU1 subsystem
    [Possible interference] Possible concurrent accesses between CPUx, CLAx and DMAx.
    All the configuration registers are accessible from CPU1 only and not by it's CLA or DMA. For peripheral access, either DMA or CLA can have access (not both, based on secondary master select).

    Ok.

    Vivek Singh said:
    Accessible by only one CPU at a time by Semaphore
    [No interference] Only CPU have accesses and only one a time.
    Not true. In some cases reads are always allowed by other CPU (e.g. EMIF).

    The different items I stated are the headings from the table in section 6.5 of the datasheet so basically this point only deals with clock and PLL.

    Vivek Singh said:
    Peripherals and Registers with Unique Copies of Registers for each CPU and CLA Master
    [No interference] Each CPU and CLA master sees the registers on its own bus and concurrent access can be performed without interference.
    That is correct but not many example like that. If you have some specific IP in mind, please let me know.

    Not sure what you meant there ?

    Clément

  • 0 in reply to Clément Letonnelier
    TI__Guru** 115431 points

    Hi,

    Vivek Singh

    Peripherals that can be assigned to CPU1 or CPU2 and have common selectable secondary masters
    [Possible interference] I believe that here concurrent access can occur between the CPU1 (or CPU2) and the selected secondary master. However, the CPU which has not been assigned doesn’t have access to these peripherals so no CPU1/CPU2 interference.
    What do you mean by "common selectable secondary masters". Both CPU have their own secondary masters (CLA/DMA) and configuration register to select the same.

    Well this is the terminology you use in the section 6.5 of the datasheet.

    But basically my question was related to the possible interference, so I guess it can occur if both the CPU and its secondary master accesses the peripheral at the same time.

    Yes, CPU and secondary master can have interference.

    Vivek Singh
    Accessible by only one CPU at a time by Semaphore
    [No interference] Only CPU have accesses and only one a time.
    Not true. In some cases reads are always allowed by other CPU (e.g. EMIF).

    The different items I stated are the headings from the table in section 6.5 of the datasheet so basically this point only deals with clock and PLL.

    Ok. Yes that is true for clock and PLL.

    Vivek Singh
    Peripherals and Registers with Unique Copies of Registers for each CPU and CLA Master
    [No interference] Each CPU and CLA master sees the registers on its own bus and concurrent access can be performed without interference.
    That is correct but not many example like that. If you have some specific IP in mind, please let me know.

    Not sure what you meant there ?

     

    I mean, we don't have many peripherals for which we have unique set of registers on CPU and secondary master. So which specific peripheral you referring in this query.
    Regards,
    Vivek Singh

  • 0 in reply to Vivek Singh
    Expert 2816 points

    Hi,

    Wrt. the latest point, I wasn't refering to a particular peripheral.

    As I said it was the extract of the headings from a table in the datasheet.

    But basically in our application this would be the ADC results.

    Anyways, I think my question was globally covered, thanks for your answers.

    Clément