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I'm working with a customer who is having SPI data corruption on the MISO line (F28004x is in SPI slave mode) at high temperatures. The investigation is ongoing, and it is not certain at this point the F280049 is implemented in the root cause. However, the Errata advisory GPIO: Signal Latch-up to Vss looks interesting.
This advisory is only supposed to affect revision 0 devices. The customer is using a TMX revision B device. Are there test coverage gaps between a TMX revision B and our production TMS revision B devices that we should be aware of when troubleshooting this issue with the customer?
Thanks,
Stuart
