TMS320F28388D: Peripheral arbitration between two C28x CPU cores

Gunter Schmer

Part Number: TMS320F28388D

Hi,

we are trying to understand some of the arbitration between CPU1 & CPU2 a little better for the TMS320F283xxD. The TRM covers arbitration for Global Shared Memories in the “Memory Controller Module” as well as peripheral arbitration in the “CPU and CLA Arbitration” section, but we are not sure what applies for peripheral arbitration between the two CPU cores.

Could you help answer some questions from the perspective of the specific scenario below?

In a scenario where the CPUSEL0 register is configured so that EPWM1 is connected to CPU1 and EPWM2 is connected to CPU2…

What happens if CPU1 attempts to access registers for EPWM1 at the same time as CPU2 attempts to access registers for EPWM2? Is concurrent access allowed? If not, what arbitration scheme is used? Does the arbitration change if one of the accesses is done by the DMA controller instead of the CPU?

Thanks!

--Gunter

over 5 years ago

0 Vivek Singh over 5 years ago

TI__Guru** 115271 points

Hi Gunter,

We are looking into your query and will get back to you soon.

Regards,

Vivek Singh

0 Vivek Singh over 5 years ago in reply to Vivek Singh

TI__Guru** 115271 points

Hi,

What happens if CPU1 attempts to access registers for EPWM1 at the same time as CPU2 attempts to access registers for EPWM2? Is concurrent access allowed?

In this case access from CPU1 and CPU2 will go simultaneously without any arbitration.

Regards,

Vivek Singh

0 Gunter Schmer over 5 years ago in reply to Vivek Singh

TI__Genius 14212 points

Hi Vivek,

to clarify, for this case, does CPU1 have its own bus to EPWM1, as well as CPU2 its own bus to EPWM2, so that these accesses can happen simultaneously concurrently?

Thanks!

--Gunter

0 Vivek Singh over 5 years ago in reply to Gunter Schmer

TI__Guru** 115271 points

Yes, both have separate bus which are muxed based CPUSEL.

Regards,

Vivek Singh

0 Jason Dallman over 5 years ago in reply to Vivek Singh

Prodigy 10 points

Does this answer apply universally to all peripherals that are identified in the CPUSELx registers? (e.g. ADC, SCI, SPI, CAN)

0 Vivek Singh over 5 years ago in reply to Jason Dallman

TI__Guru** 115271 points

That is correct. Please note that there is no CPUSEL for ADC result registers because all the masters can read them simultaneously without any arbitration.

Regards,

Vivek Singh

0 Gunter Schmer over 5 years ago in reply to Vivek Singh

TI__Genius 14212 points

Hi Vivek,

Jason was also asking if there is documentation for the exact internal bus structures and interconnects. One example of that was the CPUs accessing respective EPWM or ADCs. This more detailed interconnect description would be important for the safety assessment.

Could you point us in the right direction?

Thanks!

--Gunter

0 Vivek Singh over 5 years ago in reply to Gunter Schmer

TI__Guru** 115271 points

Hi,

Sorry for delayed response. We do not have detailed info about internal but structure and interconnects in the document. We'll discuss this and try to provide some addition detail in next revision of document.

Please let me know if you have any additional queries on this topic.

Regards,

Vivek Singh

C2000™︎ microcontrollers

C2000 microcontrollers forum

TMS320F28388D: Peripheral arbitration between two C28x CPU cores