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TMDSCNCD28388D: RAM of ARM core (CM) of TMS320F28388D, is it enough

Andrii Shevchuk
Intellectual 865 points
Part Number: TMDSCNCD28388D
Other Parts Discussed in Thread: MSP432E401Y

Hello All

I have started TCP/IP stack under SYS/BIOS (example tcpEchoF2838X  ) it works fine but,

It occupes about 62K  RAM  of the ARM core (CM - Connectivity Manager). The CM has 96K RAM totaly , 16K of them designed to the IPC communication

,so it has limited general usage(At least I am going to use it  as intended and keep common data of DSP cores and CM core and for data exchange between them ).

So generaly, We can use 80K , 62K of which are occupied. So there are left 18K for other periphery usage.

But TMS320F28388 has very developed external communication periphery - UART, 10/100 Ethernet 1588 MII/RMII, MCAN(CAN-FD), 2 CAN, USB,EtherCAT(slave). Last three are shared between CM and CPU1.

So 18K is obiously not anough for complete usage all communication periphery + internal board communication like SSI or I2C.

Roughly  USB stack 2K-10K(in depending of quantity of buffers (data exchanging intensity ) and type of exchanging bulk or isochronous ),  CAN Open about 5K- 20K one instance (in Depending from size of SDO and

quantity of PDO) , I am afraid to suppose how much the EtherCAT, MCAN and J1939 will occupy.  

Of course,   the figures are debatable. But for rough estimation valid (for my point of view).

And I did not find  the external memory interface of CM to expand range of memory.

For Example MSP432E401Y controller, with less communication periphery, has 256K RAM.

With possibility to expand it by external interface.

So I  consider the TMS320F2838D as one of the best for its field of usage but due to lack of CM memory,

it will led to  incomplete usage of communication periphery.

I can foresee several suggestions

1) Memory Optimization

My answer. Of course It is possible to optimize but how deeply ?

And for strong industrial RealTime application which has to work 24 hour a day  and has "wide bandwidth of data" - very intensive data  exchange and handling,

RAM should be enough to provide extra buffers. And decreasing these ones is at least very painful and it can lead to hard to find errors.

 2) Share communication periphery between CM and CPU1

My answer - Of course it is possible But what about the beauty and harmony of the solution.

It is very good idea to unload the DSP core from uncharacteristic  tasks and let it one only to calculate

while core of general purpose is occupied by general tasks, one of them - communication.

Due to this solution, I have selected this controller, But TI is proposing partial solution due to CM RAM lack.

3) It is not possible tu use all connections simultaliosly or usually it is not neccesary.

My answer - Of coarse it is correct for example TCP/IP and EtherCAT, or CAN and CAN- FD.

But I am going to use UART(for low-level log  ), USB, Ethernet (TCP/IP) and 2 CAN (CANOpen)   and I am lacking CM RAM.

So it is observed some disbalance between number of communication periphery and the number of CM RAM .

So the question is

Is it possible to increase internal RAM at least to 128 K, better to 176 and the best to 256K ?

Best Regards

Andrii Shevchuk

  • 0
    TI__Guru** 115271 points

    Hi Andrii,

    Thank you for providing very detailed analysis of your observation on this topic. We really appreciate this.

    You have also provided the potential solution to address the concern. I'll answer some specific query you have in this post.

    And I did not find  the external memory interface of CM to expand range of memory.

    You are correct. We do not have external interface support for CM subsystem. It is only available for CPU1/CPU2 subsystem.

    Is it possible to increase internal RAM at least to 128 K, better to 176 and the best to 256K ?

    Max internal RAM is 96KB only on CM side and it can not be increased further. I am sure you are aware that we also have 512KB of flash on CM subsystem which user should use for the application code ( and constant data). Also as you mentioned, we have mapped EtherCAT on C28x side and have SW support for that so user should be able to use that to minimize the RAM usage on CM.

    I will forward your feedback for consideration for future device to our architecture team.

    Regards,

    Vivek Singh

     

  • 0 in reply to Vivek Singh
    Intellectual 865 points

          Hi Vivek

    Thank you for your answer.

    One comment
    From my point of view, the internal RAM is preferable for many reasons.
    1) Interface with external RAM occupies the pins (These ones always are not enough). The Von Neumann architecture occupies less but requires additional address latch register and decreases the speed of data exchange. Harvard architecture requires more pins to separate address bus and data bus.
    2)A GPIOs cuts off the internal data bus and address bus from external electromagnetic noises. But with external  RAM, we open internal buses for electromagnetic noises. This one essentially decreases electromagnetic noises immunity of a device.  The device emits more as well. These ones increase efforts to PCB routing.
    3) only internal RAM  usage decrease effort of support ( if I receive a description of some incomprehensible behavior of the device, I know exactly that is not electromagnetic compatibility on system level. And it is very important because of this one very difficult to investigate  ).
    4) Price. In summary, the device with external memory has more cost than without one.   
    Therefore, I use external memory only in extreme cases for industrial embbeded solutions.

    Best Regards

    Andrii

  • 0 in reply to Andrii Shevchuk
    TI__Guru** 115271 points

    Thank you Andrii. I am sure you must have looked at possible ways to move maximum possible code/constant data to internal Flash.

    Regards,

    Vivek Singh