TMS320F28377D: Flashing firmware over SCI

Mike,

In your application linker cmd file, you can use ALIGN(8) for this purpose.  See C:\ti\c2000\C2000Ware_2_01_00_00\device_support\f2837xd\common\cmd\2837xD_FLASH_lnk_cpu1.cmd as an example.  Please use latest C2000Ware as the linker cmd files are updated recently to show this.

Thanks and regards,
Vamsi

Hello,

I tried applying align(8) to my linker cmd file but still having issues.  Are there other things that could lead to me to getting ERROR Status: PROGRAM_ERROR, ERROR Address: 0x3 when I select DFU1 in the serial flash programmer ?

Thanks!

Best,

Mike

Mike,

Can you check if there are any initialized sections mapped to RAM in your application linker cmd file?  All initialized sections should be mapped to Flash for the kernels to be able to program the content to Flash.

Thanks and regards,

Vamsi

Hi Vamsi,

This has to do with loading from flash but running on RAM right?  Just so I'm clear, for example RAMLS2 and RAMGS1_2 from sections below need to be loaded into flash using something like?  Any chance you see any other issues in SECTIONS?

ramfuncs : LOAD = FLASHD,

RUN = RAML0,

LOAD_START(_RamfuncsLoadStart),

LOAD_END(_RamfuncsLoadEnd),

RUN_START(_RamfuncsRunStart)

I pasted the sections portion of my linker cmd file below. Thanks!

Best,

Mike

SECTIONS
{
/* ------------------ Allocate program areas: ----------------------- */
codestart : > BEGIN PAGE = 0, ALIGN(8)
bootloader : > FLASHA PAGE = 0, ALIGN(8)

ramfuncs : LOAD = FLASHB,
RUN = RAMGS8,
LOAD_START(_RamfuncsLoadStart),
LOAD_SIZE(_RamfuncsLoadSize),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
RUN_SIZE(_RamfuncsRunSize),
RUN_END(_RamfuncsRunEnd),
PAGE = 0, ALIGN(8)

ramfuncs0 : LOAD = FLASHA,
RUN = RAMGS7,
LOAD_START(_Ramfuncs0LoadStart),
LOAD_SIZE(_Ramfuncs0LoadSize),
LOAD_END(_Ramfuncs0LoadEnd),
RUN_START(_Ramfuncs0RunStart),
RUN_SIZE(_Ramfuncs0RunSize),
RUN_END(_Ramfuncs0RunEnd),
PAGE = 0, ALIGN(8)

ramfuncs1 : LOAD = FLASHA,
RUN = RAMGS7,
LOAD_START(_Ramfuncs1LoadStart),
LOAD_SIZE(_Ramfuncs1LoadSize),
LOAD_END(_Ramfuncs1LoadEnd),
RUN_START(_Ramfuncs1RunStart),
RUN_SIZE(_Ramfuncs1RunSize),
RUN_END(_Ramfuncs1RunEnd),
PAGE = 0, ALIGN(8)

ramfuncs2 : LOAD = FLASHA,
RUN = RAMGS8 ,
LOAD_START(_Ramfuncs2LoadStart),
LOAD_SIZE(_Ramfuncs2LoadSize),
LOAD_END(_Ramfuncs2LoadEnd),
RUN_START(_Ramfuncs2RunStart),
RUN_SIZE(_Ramfuncs2RunSize),
RUN_END(_Ramfuncs2RunEnd),
PAGE = 0, ALIGN(8)

ramfuncs3 : LOAD = FLASHA,
RUN = RAMLS3 ,
LOAD_START(_Ramfuncs3LoadStart),
LOAD_SIZE(_Ramfuncs3LoadSize),
LOAD_END(_Ramfuncs3LoadEnd),
RUN_START(_Ramfuncs3RunStart),
RUN_SIZE(_Ramfuncs3RunSize),
RUN_END(_Ramfuncs3RunEnd),
PAGE = 0, ALIGN(8)

Cla1Prog : LOAD = FLASHC,
RUN = RAMLS4_5,//|RAMLS5,
LOAD_START(_Cla1ProgLoadStart),
LOAD_SIZE(_Cla1ProgLoadSize),
LOAD_END(_Cla1ProgLoadEnd),
RUN_START(_Cla1ProgRunStart),
RUN_SIZE(_Cla1ProgRunSize),
RUN_END(_Cla1ProgRunEnd),
PAGE = 0, ALIGN(8)

.text : > FLASHE PAGE = 0, ALIGN(8)

Initialization : > FLASHE PAGE = 0, ALIGN(8)

.cinit : LOAD = FLASHA
RUN = RAMM0 //M0
LOAD_START(_cinitLoadStart),
LOAD_SIZE(_cinitLoadSize),
LOAD_END(_cinitLoadEnd),
RUN_START(_cinitRunStart),
RUN_SIZE(_cinitRunSize),
RUN_END(_cinitRunEnd),
PAGE = 0, ALIGN(8)

.pinit : LOAD = FLASHA
RUN = RAMM0,
LOAD_START(_pinitLoadStart),
LOAD_SIZE(_pinitLoadSize),
LOAD_END(_pinitLoadEnd),
RUN_START(_pinitRunStart),
RUN_SIZE(_pinitRunSize),
RUN_END(_pinitRunEnd),
PAGE = 0, ALIGN(8)

.switch : LOAD = FLASHA
RUN = RAMM0,
LOAD_START(_switchLoadStart),
LOAD_SIZE(_switchLoadSize),
LOAD_END(_switchLoadEnd),
RUN_START(_switchRunStart),
RUN_SIZE(_switchRunSize),
RUN_END(_switchRunEnd),
PAGE = 0, ALIGN(8)
//GS1 Cpu2 to Cpu1
CPU2TOCPU1Variable : RUN = RAMGS1_2, PAGE = 1 //CPU2TOCPU1RAM
RUN_START(_CPU2TOCPU1Variable_start),
RUN_SIZE(_CPU2TOCPU1Variable_size)
RUN_END(_CPU2TOCPU1Variable2_end)

// GS14 for CPU1 to CPU2 information

VarCpu1Cpu2 : RUN = RAMGS14_2, PAGE = 1
RUN_START(_VarCpu1Cpu2_start),
RUN_SIZE(_VarCpu1Cpu2_size)
RUN_END(_VarCpu1Cpu2_end)

ParamCpu1Cpu2 : RUN = RAMGS14_3, PAGE = 1
RUN_START(_ParamCpu1Cpu2_start),
RUN_SIZE(_ParamCpu1Cpu2_size)
RUN_END(_ParamCpu1Cpu2_end)

.reset : > RESET, PAGE = 0, TYPE = DSECT

CmdTable : > FLASHB, PAGE = 0, ALIGN(8)
FcnTable : > FLASHB, PAGE = 0, ALIGN(8)

/* Initalized sections go in Flash */
// .econst : > FLASHF | FLASHG | FLASHH PAGE = 0
// .switch : > FLASHB PAGE = 0

/*----------------- Allocate uninitalized data sections:------------------ */
.stack : > RAMM1 PAGE = 1
.ebss : > RAMD1 PAGE = 1
.bss : > RAMD1 PAGE = 1
.econst : > RAMD1 PAGE = 1
.esysmem : > RAMD1 PAGE = 1
.data : > RAMD1 PAGE = 1

Filter_RegsFile : > RAMGS0, PAGE = 1

// SHARERAMGS0 : > RAMGS0, PAGE = 1
// SHARERAMGS1 : > RAMGS1, PAGE = 1

CLA1mathTables : LOAD = FLASHD /* Note for running from RAM the load and RUN can be the same */
RUN = RAMLS1,
LOAD_START(_Cla1mathTablesLoadStart),
LOAD_SIZE(_Cla1mathTablesLoadSize),
LOAD_END(_Cla1mathTablesLoadEnd),
RUN_START(_Cla1mathTablesRunStart),
RUN_SIZE(_Cla1mathTablesRunSize),
RUN_END(_Cla1mathTablesRunEnd),
PAGE = 1, ALIGN(8)

/*Data Memory*/
SPI_data : align(0x40) > RAMLS2,PAGE = 1
SCI_data : align(0x40) > RAMLS2,PAGE = 1 // Need to be in one DP
SCI_Rx : align(0x100) > RAMLS2,PAGE = 1
SCI_Tx : align(0x200) > RAMLS2,PAGE = 1

// ProfilePos : > RAMGS1, PAGE = 1
// CANOpenData : > RAMGS1, PAGE = 1

// Updated on 07-25-2017 Lily
// GS14 for CPU1 to CPU2
NV_data : align(64) RUN = RAMGS14_3, PAGE = 1 /*RAM address where parameters to be saved are stored */
END(_NV_data_end1),
RUN_START(_NV_data_start),
RUN_SIZE(_NV_data_size)
RUN_END(_NV_data_end)

NV_data_modinf : block(64) RUN = RAMGS14_3, PAGE = 1 /*RAM address where model info to be saved are stored */
RUN_START(_NV_data_modinf_start),
RUN_SIZE(_NV_data_modinf_size)
RUN_END(_NV_data_modinf_end)

NV_data_ioffsets : block(64) RUN = RAMGS14_3, PAGE = 1
RUN_START(_NV_data_ioffsets_start),
RUN_SIZE(_NV_data_ioffsets_size)
RUN_END(_NV_data_ioffsets_end)

NV_data_lastf : RUN = RAMGS14_3, PAGE = 1
RUN_START(_NV_data_lastf_start),
RUN_SIZE(_NV_data_lastf_size)
RUN_END(_NV_data_lastf_end)

ProfileData : RUN = RAMGS14_3, PAGE = 1
RUN_START(_ProfileData_start),
RUN_SIZE(_ProfileData_size)
RUN_END(_ProfileData_end)

/* The following section definitions are required when using the IPC API Drivers */
GROUP : > CPU1TOCPU2RAM, PAGE = 1
{
PUTBUFFER
PUTWRITEIDX
GETREADIDX
}

GROUP : > CPU2TOCPU1RAM, PAGE = 1
{
GETBUFFER : TYPE = DSECT
GETWRITEIDX : TYPE = DSECT
PUTREADIDX : TYPE = DSECT
}

/* The following section definition are for SDFM examples */
/*
Filter1_RegsFile : > RAMGS1, PAGE = 1, fill=0x1111
Filter2_RegsFile : > RAMGS2, PAGE = 1, fill=0x2222
Filter3_RegsFile : > RAMGS3, PAGE = 1, fill=0x3333
Filter4_RegsFile : > RAMGS4, PAGE = 1, fill=0x4444
Difference_RegsFile : >RAMGS5, PAGE = 1, fill=0x3333
*/

/* CLA specific sections */
/* Cla1Prog : > RAMLS5, PAGE=0*/

// CLADataLS0 : > RAMLS0, PAGE=1
// CLADataLS5 : > RAMLS5, PAGE=1
CLADataLS1 : > RAMLS1, PAGE=1, ALIGN(8)

/*CLA1 and CPU1 shared Data memory*/
Cla1Cpu1ShareLSR : > RAMLS1, PAGE=1, ALIGN(8)

Cla1ToCpuMsgRAM : > CLA1_MSGRAMLOW, PAGE = 1, ALIGN(8)
CpuToCla1MsgRAM : > CLA1_MSGRAMHIGH, PAGE = 1, ALIGN(8)

#ifdef CLA_C
/* CLA C compiler sections */
//
// Must be allocated to memory the CLA has write access to
//
CLAscratch :
{ *.obj(CLAscratch)
. += CLA_SCRATCHPAD_SIZE;
*.obj(CLAscratch_end) } > RAMLS1, PAGE = 1, ALIGN(8)

.scratchpad : > RAMLS1, PAGE = 1
.bss_cla : > RAMLS1, PAGE = 1
.const_cla : > RAMLS1, PAGE = 1
CLA1mathTables : > RAMLS1, PAGE = 1
#endif //CLA_C

}

Mike,

I am hoping this debugs is closed.  I am closing this post.

I am not available until March 9th.  If you have further questions, please open a new post and our team will help you further.

Thanks and regards,

Vamsi