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TMS320F28388D: ADC configuration restrictions for synchronization

Jennifer Stander
Intellectual 510 points
Part Number: TMS320F28388D

Hi,

It looks like there are some tricky synchronization requirements across all 4 ADCs and just wanted to make sure this was OK.

If ADC-A & B are configured for 12-bit single ended and ADC-C & D for 16-bit differential. They can be configured once at the beginning and left that way as long as their conversions do not over lap in time. 

The data sheet current just says no supported for Asynchronous operation instead of giving a performance number. I know the part is preliminary... Will the situation in Figure 20-21 of the TRM where ADC-A is 12 bit and ADC-B is 16-bit and they have the same S+H time and same trigger but finish at different times ever be supported or its performance degradation spec'ed.

Thanks,

Jennifer

  • 0
    TI__Guru 60865 points

    Hi Jennifer,

    Yes, if the conversions don't overlap in time, then the performance for the 12-bit and 16-bit ADCs will each meet their DS rated performance specifications for 'synchronous'. 

    We do not plan to specify the specific performance degradation beyond what is currently in the datasheet.  Under the conditions where noise couples from one ADC to another due to simultaneous but non lock-step operation, the absolute disturbance magnitude is constant for both 16-bit and 12-bit modes.  The performance in absolute terms is therefore similar in these circumstances between 12-bit and 16-bit mode, negating the advantage of setting the ADC into 16-bit mode. 

    Definitely understand that this can make setup of the sampling scheme tricky; we're happy to review your sampling scheme based on your sampling requirements.